/*
 * Copyright (c) Huawei Technologies Co., Ltd. 2019-2022. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * Description:
 * Author: huawei
 * Create: 2019-10-15
 */

#ifndef IO_SUBCTRL_REG_OFFSET_FIELD_H
#define IO_SUBCTRL_REG_OFFSET_FIELD_H

#define IO_SUBCTRL_ICG_EN_SMMU_TCU_LEN    1
#define IO_SUBCTRL_ICG_EN_SMMU_TCU_OFFSET 1
#define IO_SUBCTRL_ICG_EN_SMMU_TBU_LEN    1
#define IO_SUBCTRL_ICG_EN_SMMU_TBU_OFFSET 0

#define IO_SUBCTRL_ICG_DIS_SMMU_TCU_LEN    1
#define IO_SUBCTRL_ICG_DIS_SMMU_TCU_OFFSET 1
#define IO_SUBCTRL_ICG_DIS_SMMU_TBU_LEN    1
#define IO_SUBCTRL_ICG_DIS_SMMU_TBU_OFFSET 0

#define IO_SUBCTRL_ICG_EN_GPIO_DB_LEN    1
#define IO_SUBCTRL_ICG_EN_GPIO_DB_OFFSET 2
#define IO_SUBCTRL_ICG_EN_GPIO_LEN       2
#define IO_SUBCTRL_ICG_EN_GPIO_OFFSET    0

#define IO_SUBCTRL_ICG_DIS_GPIO_DB_LEN    1
#define IO_SUBCTRL_ICG_DIS_GPIO_DB_OFFSET 2
#define IO_SUBCTRL_ICG_DIS_GPIO_LEN       2
#define IO_SUBCTRL_ICG_DIS_GPIO_OFFSET    0

#define IO_SUBCTRL_ICG_EN_APB_IO_MUX_LEN    1
#define IO_SUBCTRL_ICG_EN_APB_IO_MUX_OFFSET 0

#define IO_SUBCTRL_ICG_DIS_APB_IO_MUX_LEN    1
#define IO_SUBCTRL_ICG_DIS_APB_IO_MUX_OFFSET 0

#define IO_SUBCTRL_ICG_EN_PROBE_LEN    1
#define IO_SUBCTRL_ICG_EN_PROBE_OFFSET 0

#define IO_SUBCTRL_ICG_DIS_PROBE_LEN    1
#define IO_SUBCTRL_ICG_DIS_PROBE_OFFSET 0

#define IO_SUBCTRL_ICG_EN_MDIO_LEN    2
#define IO_SUBCTRL_ICG_EN_MDIO_OFFSET 0

#define IO_SUBCTRL_ICG_DIS_MDIO_LEN    2
#define IO_SUBCTRL_ICG_DIS_MDIO_OFFSET 0

#define IO_SUBCTRL_ICG_EN_HILINK0_PMA_RX_LEN    4
#define IO_SUBCTRL_ICG_EN_HILINK0_PMA_RX_OFFSET 10
#define IO_SUBCTRL_ICG_EN_HILINK0_PMA_TX_LEN    4
#define IO_SUBCTRL_ICG_EN_HILINK0_PMA_TX_OFFSET 6
#define IO_SUBCTRL_ICG_EN_HILINK0_RXOCLK_LEN    4
#define IO_SUBCTRL_ICG_EN_HILINK0_RXOCLK_OFFSET 2
#define IO_SUBCTRL_ICG_EN_HILINK0_MCLK_LEN      2
#define IO_SUBCTRL_ICG_EN_HILINK0_MCLK_OFFSET   0

#define IO_SUBCTRL_ICG_DIS_HILINK0_PMA_RX_LEN    4
#define IO_SUBCTRL_ICG_DIS_HILINK0_PMA_RX_OFFSET 10
#define IO_SUBCTRL_ICG_DIS_HILINK0_PMA_TX_LEN    4
#define IO_SUBCTRL_ICG_DIS_HILINK0_PMA_TX_OFFSET 6
#define IO_SUBCTRL_ICG_DIS_HILINK0_RXOCLK_LEN    4
#define IO_SUBCTRL_ICG_DIS_HILINK0_RXOCLK_OFFSET 2
#define IO_SUBCTRL_ICG_DIS_HILINK0_MCLK_LEN      2
#define IO_SUBCTRL_ICG_DIS_HILINK0_MCLK_OFFSET   0

#define IO_SUBCTRL_ICG_EN_HILINK1_PMA_RX_LEN    4
#define IO_SUBCTRL_ICG_EN_HILINK1_PMA_RX_OFFSET 10
#define IO_SUBCTRL_ICG_EN_HILINK1_PMA_TX_LEN    4
#define IO_SUBCTRL_ICG_EN_HILINK1_PMA_TX_OFFSET 6
#define IO_SUBCTRL_ICG_EN_HILINK1_RXOCLK_LEN    4
#define IO_SUBCTRL_ICG_EN_HILINK1_RXOCLK_OFFSET 2
#define IO_SUBCTRL_ICG_EN_HILINK1_MCLK_LEN      2
#define IO_SUBCTRL_ICG_EN_HILINK1_MCLK_OFFSET   0

#define IO_SUBCTRL_ICG_DIS_HILINK1_PMA_RX_LEN    4
#define IO_SUBCTRL_ICG_DIS_HILINK1_PMA_RX_OFFSET 10
#define IO_SUBCTRL_ICG_DIS_HILINK1_PMA_TX_LEN    4
#define IO_SUBCTRL_ICG_DIS_HILINK1_PMA_TX_OFFSET 6
#define IO_SUBCTRL_ICG_DIS_HILINK1_RXOCLK_LEN    4
#define IO_SUBCTRL_ICG_DIS_HILINK1_RXOCLK_OFFSET 2
#define IO_SUBCTRL_ICG_DIS_HILINK1_MCLK_LEN      2
#define IO_SUBCTRL_ICG_DIS_HILINK1_MCLK_OFFSET   0

#define IO_SUBCTRL_ICG_EN_SDS_SYS_CLK_LEN    2
#define IO_SUBCTRL_ICG_EN_SDS_SYS_CLK_OFFSET 0

#define IO_SUBCTRL_ICG_DIS_SDS_SYS_CLK_LEN    2
#define IO_SUBCTRL_ICG_DIS_SDS_SYS_CLK_OFFSET 0

#define IO_SUBCTRL_ICG_EN_PCIE_SLV_LEN    1
#define IO_SUBCTRL_ICG_EN_PCIE_SLV_OFFSET 1
#define IO_SUBCTRL_ICG_EN_PCIE_MST_LEN    1
#define IO_SUBCTRL_ICG_EN_PCIE_MST_OFFSET 0

#define IO_SUBCTRL_ICG_DIS_PCIE_SLV_LEN    1
#define IO_SUBCTRL_ICG_DIS_PCIE_SLV_OFFSET 1
#define IO_SUBCTRL_ICG_DIS_PCIE_MST_LEN    1
#define IO_SUBCTRL_ICG_DIS_PCIE_MST_OFFSET 0

#define IO_SUBCTRL_ICG_EN_PCIE0_CLK_TL_AXI_LEN           1
#define IO_SUBCTRL_ICG_EN_PCIE0_CLK_TL_AXI_OFFSET        31
#define IO_SUBCTRL_ICG_EN_PCIE0_CLK_AP_AXI_LEN           5
#define IO_SUBCTRL_ICG_EN_PCIE0_CLK_AP_AXI_OFFSET        26
#define IO_SUBCTRL_ICG_EN_PCIE0_CLK_APB_LEN              2
#define IO_SUBCTRL_ICG_EN_PCIE0_CLK_APB_OFFSET           24
#define IO_SUBCTRL_ICG_EN_PCIE0_CLK_CORE_PHY_LANE_LEN    4
#define IO_SUBCTRL_ICG_EN_PCIE0_CLK_CORE_PHY_LANE_OFFSET 20
#define IO_SUBCTRL_ICG_EN_PCIE0_CLK_PCS_LOGIC_LEN        4
#define IO_SUBCTRL_ICG_EN_PCIE0_CLK_PCS_LOGIC_OFFSET     16
#define IO_SUBCTRL_ICG_EN_PCIE0_CLK_PCS_LOGIC_DIV_LEN    4
#define IO_SUBCTRL_ICG_EN_PCIE0_CLK_PCS_LOGIC_DIV_OFFSET 12
#define IO_SUBCTRL_ICG_EN_PCIE0_CLK_PCS_RX_LEN           4
#define IO_SUBCTRL_ICG_EN_PCIE0_CLK_PCS_RX_OFFSET        8
#define IO_SUBCTRL_ICG_EN_PCIE0_CLK_PCS_TX_LEN           4
#define IO_SUBCTRL_ICG_EN_PCIE0_CLK_PCS_TX_OFFSET        4
#define IO_SUBCTRL_ICG_EN_PCIE0_CLK_PIPE_LANE_LEN        4
#define IO_SUBCTRL_ICG_EN_PCIE0_CLK_PIPE_LANE_OFFSET     0

#define IO_SUBCTRL_ICG_DIS_PCIE0_CLK_TL_AXI_LEN           1
#define IO_SUBCTRL_ICG_DIS_PCIE0_CLK_TL_AXI_OFFSET        31
#define IO_SUBCTRL_ICG_DIS_PCIE0_CLK_AP_AXI_LEN           5
#define IO_SUBCTRL_ICG_DIS_PCIE0_CLK_AP_AXI_OFFSET        26
#define IO_SUBCTRL_ICG_DIS_PCIE0_CLK_APB_LEN              2
#define IO_SUBCTRL_ICG_DIS_PCIE0_CLK_APB_OFFSET           24
#define IO_SUBCTRL_ICG_DIS_PCIE0_CLK_CORE_PHY_LANE_LEN    4
#define IO_SUBCTRL_ICG_DIS_PCIE0_CLK_CORE_PHY_LANE_OFFSET 20
#define IO_SUBCTRL_ICG_DIS_PCIE0_CLK_PCS_LOGIC_LEN        4
#define IO_SUBCTRL_ICG_DIS_PCIE0_CLK_PCS_LOGIC_OFFSET     16
#define IO_SUBCTRL_ICG_DIS_PCIE0_CLK_PCS_LOGIC_DIV_LEN    4
#define IO_SUBCTRL_ICG_DIS_PCIE0_CLK_PCS_LOGIC_DIV_OFFSET 12
#define IO_SUBCTRL_ICG_DIS_PCIE0_CLK_PCS_RX_LEN           4
#define IO_SUBCTRL_ICG_DIS_PCIE0_CLK_PCS_RX_OFFSET        8
#define IO_SUBCTRL_ICG_DIS_PCIE0_CLK_PCS_TX_LEN           4
#define IO_SUBCTRL_ICG_DIS_PCIE0_CLK_PCS_TX_OFFSET        4
#define IO_SUBCTRL_ICG_DIS_PCIE0_CLK_PIPE_LANE_LEN        4
#define IO_SUBCTRL_ICG_DIS_PCIE0_CLK_PIPE_LANE_OFFSET     0

#define IO_SUBCTRL_ICG_EN_PCIE0_CLK_CORE_PHY_COMMON_LEN      1
#define IO_SUBCTRL_ICG_EN_PCIE0_CLK_CORE_PHY_COMMON_OFFSET   7
#define IO_SUBCTRL_ICG_EN_PCIE0_CLK_CORE_PHY_PORT_LEN        1
#define IO_SUBCTRL_ICG_EN_PCIE0_CLK_CORE_PHY_PORT_OFFSET     6
#define IO_SUBCTRL_ICG_EN_PCIE0_CLK_CORE_PHY_PORT_DIV_LEN    1
#define IO_SUBCTRL_ICG_EN_PCIE0_CLK_CORE_PHY_PORT_DIV_OFFSET 5
#define IO_SUBCTRL_ICG_EN_PCIE0_CLK_CORE_TL_COMMON_LEN       1
#define IO_SUBCTRL_ICG_EN_PCIE0_CLK_CORE_TL_COMMON_OFFSET    4
#define IO_SUBCTRL_ICG_EN_PCIE0_CLK_CORE_TL_PORT_LEN         1
#define IO_SUBCTRL_ICG_EN_PCIE0_CLK_CORE_TL_PORT_OFFSET      3
#define IO_SUBCTRL_ICG_EN_PCIE0_CLK_CORE_TL_PORT_DIV_LEN     1
#define IO_SUBCTRL_ICG_EN_PCIE0_CLK_CORE_TL_PORT_DIV_OFFSET  2
#define IO_SUBCTRL_ICG_EN_PCIE0_CLK_PCS_APB_LEN              1
#define IO_SUBCTRL_ICG_EN_PCIE0_CLK_PCS_APB_OFFSET           1
#define IO_SUBCTRL_ICG_EN_PCIE0_CLK_PCS_LOGIC_COMMON_LEN     1
#define IO_SUBCTRL_ICG_EN_PCIE0_CLK_PCS_LOGIC_COMMON_OFFSET  0

#define IO_SUBCTRL_ICG_DIS_PCIE0_CLK_CORE_PHY_COMMON_LEN      1
#define IO_SUBCTRL_ICG_DIS_PCIE0_CLK_CORE_PHY_COMMON_OFFSET   7
#define IO_SUBCTRL_ICG_DIS_PCIE0_CLK_CORE_PHY_PORT_LEN        1
#define IO_SUBCTRL_ICG_DIS_PCIE0_CLK_CORE_PHY_PORT_OFFSET     6
#define IO_SUBCTRL_ICG_DIS_PCIE0_CLK_CORE_PHY_PORT_DIV_LEN    1
#define IO_SUBCTRL_ICG_DIS_PCIE0_CLK_CORE_PHY_PORT_DIV_OFFSET 5
#define IO_SUBCTRL_ICG_DIS_PCIE0_CLK_CORE_TL_COMMON_LEN       1
#define IO_SUBCTRL_ICG_DIS_PCIE0_CLK_CORE_TL_COMMON_OFFSET    4
#define IO_SUBCTRL_ICG_DIS_PCIE0_CLK_CORE_TL_PORT_LEN         1
#define IO_SUBCTRL_ICG_DIS_PCIE0_CLK_CORE_TL_PORT_OFFSET      3
#define IO_SUBCTRL_ICG_DIS_PCIE0_CLK_CORE_TL_PORT_DIV_LEN     1
#define IO_SUBCTRL_ICG_DIS_PCIE0_CLK_CORE_TL_PORT_DIV_OFFSET  2
#define IO_SUBCTRL_ICG_DIS_PCIE0_CLK_PCS_APB_LEN              1
#define IO_SUBCTRL_ICG_DIS_PCIE0_CLK_PCS_APB_OFFSET           1
#define IO_SUBCTRL_ICG_DIS_PCIE0_CLK_PCS_LOGIC_COMMON_LEN     1
#define IO_SUBCTRL_ICG_DIS_PCIE0_CLK_PCS_LOGIC_COMMON_OFFSET  0

#define IO_SUBCTRL_ICG_EN_PCIE1_CLK_TL_AXI_LEN           1
#define IO_SUBCTRL_ICG_EN_PCIE1_CLK_TL_AXI_OFFSET        31
#define IO_SUBCTRL_ICG_EN_PCIE1_CLK_AP_AXI_LEN           5
#define IO_SUBCTRL_ICG_EN_PCIE1_CLK_AP_AXI_OFFSET        26
#define IO_SUBCTRL_ICG_EN_PCIE1_CLK_APB_LEN              2
#define IO_SUBCTRL_ICG_EN_PCIE1_CLK_APB_OFFSET           24
#define IO_SUBCTRL_ICG_EN_PCIE1_CLK_CORE_PHY_LANE_LEN    4
#define IO_SUBCTRL_ICG_EN_PCIE1_CLK_CORE_PHY_LANE_OFFSET 20
#define IO_SUBCTRL_ICG_EN_PCIE1_CLK_PCS_LOGIC_LEN        4
#define IO_SUBCTRL_ICG_EN_PCIE1_CLK_PCS_LOGIC_OFFSET     16
#define IO_SUBCTRL_ICG_EN_PCIE1_CLK_PCS_LOGIC_DIV_LEN    4
#define IO_SUBCTRL_ICG_EN_PCIE1_CLK_PCS_LOGIC_DIV_OFFSET 12
#define IO_SUBCTRL_ICG_EN_PCIE1_CLK_PCS_RX_LEN           4
#define IO_SUBCTRL_ICG_EN_PCIE1_CLK_PCS_RX_OFFSET        8
#define IO_SUBCTRL_ICG_EN_PCIE1_CLK_PCS_TX_LEN           4
#define IO_SUBCTRL_ICG_EN_PCIE1_CLK_PCS_TX_OFFSET        4
#define IO_SUBCTRL_ICG_EN_PCIE1_CLK_PIPE_LANE_LEN        4
#define IO_SUBCTRL_ICG_EN_PCIE1_CLK_PIPE_LANE_OFFSET     0

#define IO_SUBCTRL_ICG_DIS_PCIE1_CLK_TL_AXI_LEN           1
#define IO_SUBCTRL_ICG_DIS_PCIE1_CLK_TL_AXI_OFFSET        31
#define IO_SUBCTRL_ICG_DIS_PCIE1_CLK_AP_AXI_LEN           5
#define IO_SUBCTRL_ICG_DIS_PCIE1_CLK_AP_AXI_OFFSET        26
#define IO_SUBCTRL_ICG_DIS_PCIE1_CLK_APB_LEN              2
#define IO_SUBCTRL_ICG_DIS_PCIE1_CLK_APB_OFFSET           24
#define IO_SUBCTRL_ICG_DIS_PCIE1_CLK_CORE_PHY_LANE_LEN    4
#define IO_SUBCTRL_ICG_DIS_PCIE1_CLK_CORE_PHY_LANE_OFFSET 20
#define IO_SUBCTRL_ICG_DIS_PCIE1_CLK_PCS_LOGIC_LEN        4
#define IO_SUBCTRL_ICG_DIS_PCIE1_CLK_PCS_LOGIC_OFFSET     16
#define IO_SUBCTRL_ICG_DIS_PCIE1_CLK_PCS_LOGIC_DIV_LEN    4
#define IO_SUBCTRL_ICG_DIS_PCIE1_CLK_PCS_LOGIC_DIV_OFFSET 12
#define IO_SUBCTRL_ICG_DIS_PCIE1_CLK_PCS_RX_LEN           4
#define IO_SUBCTRL_ICG_DIS_PCIE1_CLK_PCS_RX_OFFSET        8
#define IO_SUBCTRL_ICG_DIS_PCIE1_CLK_PCS_TX_LEN           4
#define IO_SUBCTRL_ICG_DIS_PCIE1_CLK_PCS_TX_OFFSET        4
#define IO_SUBCTRL_ICG_DIS_PCIE1_CLK_PIPE_LANE_LEN        4
#define IO_SUBCTRL_ICG_DIS_PCIE1_CLK_PIPE_LANE_OFFSET     0

#define IO_SUBCTRL_ICG_EN_PCIE1_CLK_CORE_PHY_COMMON_LEN      1
#define IO_SUBCTRL_ICG_EN_PCIE1_CLK_CORE_PHY_COMMON_OFFSET   7
#define IO_SUBCTRL_ICG_EN_PCIE1_CLK_CORE_PHY_PORT_LEN        1
#define IO_SUBCTRL_ICG_EN_PCIE1_CLK_CORE_PHY_PORT_OFFSET     6
#define IO_SUBCTRL_ICG_EN_PCIE1_CLK_CORE_PHY_PORT_DIV_LEN    1
#define IO_SUBCTRL_ICG_EN_PCIE1_CLK_CORE_PHY_PORT_DIV_OFFSET 5
#define IO_SUBCTRL_ICG_EN_PCIE1_CLK_CORE_TL_COMMON_LEN       1
#define IO_SUBCTRL_ICG_EN_PCIE1_CLK_CORE_TL_COMMON_OFFSET    4
#define IO_SUBCTRL_ICG_EN_PCIE1_CLK_CORE_TL_PORT_LEN         1
#define IO_SUBCTRL_ICG_EN_PCIE1_CLK_CORE_TL_PORT_OFFSET      3
#define IO_SUBCTRL_ICG_EN_PCIE1_CLK_CORE_TL_PORT_DIV_LEN     1
#define IO_SUBCTRL_ICG_EN_PCIE1_CLK_CORE_TL_PORT_DIV_OFFSET  2
#define IO_SUBCTRL_ICG_EN_PCIE1_CLK_PCS_APB_LEN              1
#define IO_SUBCTRL_ICG_EN_PCIE1_CLK_PCS_APB_OFFSET           1
#define IO_SUBCTRL_ICG_EN_PCIE1_CLK_PCS_LOGIC_COMMON_LEN     1
#define IO_SUBCTRL_ICG_EN_PCIE1_CLK_PCS_LOGIC_COMMON_OFFSET  0

#define IO_SUBCTRL_ICG_DIS_PCIE1_CLK_CORE_PHY_COMMON_LEN      1
#define IO_SUBCTRL_ICG_DIS_PCIE1_CLK_CORE_PHY_COMMON_OFFSET   7
#define IO_SUBCTRL_ICG_DIS_PCIE1_CLK_CORE_PHY_PORT_LEN        1
#define IO_SUBCTRL_ICG_DIS_PCIE1_CLK_CORE_PHY_PORT_OFFSET     6
#define IO_SUBCTRL_ICG_DIS_PCIE1_CLK_CORE_PHY_PORT_DIV_LEN    1
#define IO_SUBCTRL_ICG_DIS_PCIE1_CLK_CORE_PHY_PORT_DIV_OFFSET 5
#define IO_SUBCTRL_ICG_DIS_PCIE1_CLK_CORE_TL_COMMON_LEN       1
#define IO_SUBCTRL_ICG_DIS_PCIE1_CLK_CORE_TL_COMMON_OFFSET    4
#define IO_SUBCTRL_ICG_DIS_PCIE1_CLK_CORE_TL_PORT_LEN         1
#define IO_SUBCTRL_ICG_DIS_PCIE1_CLK_CORE_TL_PORT_OFFSET      3
#define IO_SUBCTRL_ICG_DIS_PCIE1_CLK_CORE_TL_PORT_DIV_LEN     1
#define IO_SUBCTRL_ICG_DIS_PCIE1_CLK_CORE_TL_PORT_DIV_OFFSET  2
#define IO_SUBCTRL_ICG_DIS_PCIE1_CLK_PCS_APB_LEN              1
#define IO_SUBCTRL_ICG_DIS_PCIE1_CLK_PCS_APB_OFFSET           1
#define IO_SUBCTRL_ICG_DIS_PCIE1_CLK_PCS_LOGIC_COMMON_LEN     1
#define IO_SUBCTRL_ICG_DIS_PCIE1_CLK_PCS_LOGIC_COMMON_OFFSET  0

#define IO_SUBCTRL_ICG_EN_PCIE2_CLK_TL_AXI_LEN           1
#define IO_SUBCTRL_ICG_EN_PCIE2_CLK_TL_AXI_OFFSET        31
#define IO_SUBCTRL_ICG_EN_PCIE2_CLK_AP_AXI_LEN           5
#define IO_SUBCTRL_ICG_EN_PCIE2_CLK_AP_AXI_OFFSET        26
#define IO_SUBCTRL_ICG_EN_PCIE2_CLK_APB_LEN              2
#define IO_SUBCTRL_ICG_EN_PCIE2_CLK_APB_OFFSET           24
#define IO_SUBCTRL_ICG_EN_PCIE2_CLK_CORE_PHY_LANE_LEN    4
#define IO_SUBCTRL_ICG_EN_PCIE2_CLK_CORE_PHY_LANE_OFFSET 20
#define IO_SUBCTRL_ICG_EN_PCIE2_CLK_PCS_LOGIC_LEN        4
#define IO_SUBCTRL_ICG_EN_PCIE2_CLK_PCS_LOGIC_OFFSET     16
#define IO_SUBCTRL_ICG_EN_PCIE2_CLK_PCS_LOGIC_DIV_LEN    4
#define IO_SUBCTRL_ICG_EN_PCIE2_CLK_PCS_LOGIC_DIV_OFFSET 12
#define IO_SUBCTRL_ICG_EN_PCIE2_CLK_PCS_RX_LEN           4
#define IO_SUBCTRL_ICG_EN_PCIE2_CLK_PCS_RX_OFFSET        8
#define IO_SUBCTRL_ICG_EN_PCIE2_CLK_PCS_TX_LEN           4
#define IO_SUBCTRL_ICG_EN_PCIE2_CLK_PCS_TX_OFFSET        4
#define IO_SUBCTRL_ICG_EN_PCIE2_CLK_PIPE_LANE_LEN        4
#define IO_SUBCTRL_ICG_EN_PCIE2_CLK_PIPE_LANE_OFFSET     0

#define IO_SUBCTRL_ICG_DIS_PCIE2_CLK_TL_AXI_LEN           1
#define IO_SUBCTRL_ICG_DIS_PCIE2_CLK_TL_AXI_OFFSET        31
#define IO_SUBCTRL_ICG_DIS_PCIE2_CLK_AP_AXI_LEN           5
#define IO_SUBCTRL_ICG_DIS_PCIE2_CLK_AP_AXI_OFFSET        26
#define IO_SUBCTRL_ICG_DIS_PCIE2_CLK_APB_LEN              2
#define IO_SUBCTRL_ICG_DIS_PCIE2_CLK_APB_OFFSET           24
#define IO_SUBCTRL_ICG_DIS_PCIE2_CLK_CORE_PHY_LANE_LEN    4
#define IO_SUBCTRL_ICG_DIS_PCIE2_CLK_CORE_PHY_LANE_OFFSET 20
#define IO_SUBCTRL_ICG_DIS_PCIE2_CLK_PCS_LOGIC_LEN        4
#define IO_SUBCTRL_ICG_DIS_PCIE2_CLK_PCS_LOGIC_OFFSET     16
#define IO_SUBCTRL_ICG_DIS_PCIE2_CLK_PCS_LOGIC_DIV_LEN    4
#define IO_SUBCTRL_ICG_DIS_PCIE2_CLK_PCS_LOGIC_DIV_OFFSET 12
#define IO_SUBCTRL_ICG_DIS_PCIE2_CLK_PCS_RX_LEN           4
#define IO_SUBCTRL_ICG_DIS_PCIE2_CLK_PCS_RX_OFFSET        8
#define IO_SUBCTRL_ICG_DIS_PCIE2_CLK_PCS_TX_LEN           4
#define IO_SUBCTRL_ICG_DIS_PCIE2_CLK_PCS_TX_OFFSET        4
#define IO_SUBCTRL_ICG_DIS_PCIE2_CLK_PIPE_LANE_LEN        4
#define IO_SUBCTRL_ICG_DIS_PCIE2_CLK_PIPE_LANE_OFFSET     0

#define IO_SUBCTRL_ICG_EN_PCIE2_CLK_CORE_PHY_COMMON_LEN      1
#define IO_SUBCTRL_ICG_EN_PCIE2_CLK_CORE_PHY_COMMON_OFFSET   7
#define IO_SUBCTRL_ICG_EN_PCIE2_CLK_CORE_PHY_PORT_LEN        1
#define IO_SUBCTRL_ICG_EN_PCIE2_CLK_CORE_PHY_PORT_OFFSET     6
#define IO_SUBCTRL_ICG_EN_PCIE2_CLK_CORE_PHY_PORT_DIV_LEN    1
#define IO_SUBCTRL_ICG_EN_PCIE2_CLK_CORE_PHY_PORT_DIV_OFFSET 5
#define IO_SUBCTRL_ICG_EN_PCIE2_CLK_CORE_TL_COMMON_LEN       1
#define IO_SUBCTRL_ICG_EN_PCIE2_CLK_CORE_TL_COMMON_OFFSET    4
#define IO_SUBCTRL_ICG_EN_PCIE2_CLK_CORE_TL_PORT_LEN         1
#define IO_SUBCTRL_ICG_EN_PCIE2_CLK_CORE_TL_PORT_OFFSET      3
#define IO_SUBCTRL_ICG_EN_PCIE2_CLK_CORE_TL_PORT_DIV_LEN     1
#define IO_SUBCTRL_ICG_EN_PCIE2_CLK_CORE_TL_PORT_DIV_OFFSET  2
#define IO_SUBCTRL_ICG_EN_PCIE2_CLK_PCS_APB_LEN              1
#define IO_SUBCTRL_ICG_EN_PCIE2_CLK_PCS_APB_OFFSET           1
#define IO_SUBCTRL_ICG_EN_PCIE2_CLK_PCS_LOGIC_COMMON_LEN     1
#define IO_SUBCTRL_ICG_EN_PCIE2_CLK_PCS_LOGIC_COMMON_OFFSET  0

#define IO_SUBCTRL_ICG_DIS_PCIE2_CLK_CORE_PHY_COMMON_LEN      1
#define IO_SUBCTRL_ICG_DIS_PCIE2_CLK_CORE_PHY_COMMON_OFFSET   7
#define IO_SUBCTRL_ICG_DIS_PCIE2_CLK_CORE_PHY_PORT_LEN        1
#define IO_SUBCTRL_ICG_DIS_PCIE2_CLK_CORE_PHY_PORT_OFFSET     6
#define IO_SUBCTRL_ICG_DIS_PCIE2_CLK_CORE_PHY_PORT_DIV_LEN    1
#define IO_SUBCTRL_ICG_DIS_PCIE2_CLK_CORE_PHY_PORT_DIV_OFFSET 5
#define IO_SUBCTRL_ICG_DIS_PCIE2_CLK_CORE_TL_COMMON_LEN       1
#define IO_SUBCTRL_ICG_DIS_PCIE2_CLK_CORE_TL_COMMON_OFFSET    4
#define IO_SUBCTRL_ICG_DIS_PCIE2_CLK_CORE_TL_PORT_LEN         1
#define IO_SUBCTRL_ICG_DIS_PCIE2_CLK_CORE_TL_PORT_OFFSET      3
#define IO_SUBCTRL_ICG_DIS_PCIE2_CLK_CORE_TL_PORT_DIV_LEN     1
#define IO_SUBCTRL_ICG_DIS_PCIE2_CLK_CORE_TL_PORT_DIV_OFFSET  2
#define IO_SUBCTRL_ICG_DIS_PCIE2_CLK_PCS_APB_LEN              1
#define IO_SUBCTRL_ICG_DIS_PCIE2_CLK_PCS_APB_OFFSET           1
#define IO_SUBCTRL_ICG_DIS_PCIE2_CLK_PCS_LOGIC_COMMON_LEN     1
#define IO_SUBCTRL_ICG_DIS_PCIE2_CLK_PCS_LOGIC_COMMON_OFFSET  0

#define IO_SUBCTRL_ICG_EN_PCIE3_CLK_TL_AXI_LEN           1
#define IO_SUBCTRL_ICG_EN_PCIE3_CLK_TL_AXI_OFFSET        31
#define IO_SUBCTRL_ICG_EN_PCIE3_CLK_AP_AXI_LEN           5
#define IO_SUBCTRL_ICG_EN_PCIE3_CLK_AP_AXI_OFFSET        26
#define IO_SUBCTRL_ICG_EN_PCIE3_CLK_APB_LEN              2
#define IO_SUBCTRL_ICG_EN_PCIE3_CLK_APB_OFFSET           24
#define IO_SUBCTRL_ICG_EN_PCIE3_CLK_CORE_PHY_LANE_LEN    4
#define IO_SUBCTRL_ICG_EN_PCIE3_CLK_CORE_PHY_LANE_OFFSET 20
#define IO_SUBCTRL_ICG_EN_PCIE3_CLK_PCS_LOGIC_LEN        4
#define IO_SUBCTRL_ICG_EN_PCIE3_CLK_PCS_LOGIC_OFFSET     16
#define IO_SUBCTRL_ICG_EN_PCIE3_CLK_PCS_LOGIC_DIV_LEN    4
#define IO_SUBCTRL_ICG_EN_PCIE3_CLK_PCS_LOGIC_DIV_OFFSET 12
#define IO_SUBCTRL_ICG_EN_PCIE3_CLK_PCS_RX_LEN           4
#define IO_SUBCTRL_ICG_EN_PCIE3_CLK_PCS_RX_OFFSET        8
#define IO_SUBCTRL_ICG_EN_PCIE3_CLK_PCS_TX_LEN           4
#define IO_SUBCTRL_ICG_EN_PCIE3_CLK_PCS_TX_OFFSET        4
#define IO_SUBCTRL_ICG_EN_PCIE3_CLK_PIPE_LANE_LEN        4
#define IO_SUBCTRL_ICG_EN_PCIE3_CLK_PIPE_LANE_OFFSET     0

#define IO_SUBCTRL_ICG_DIS_PCIE3_CLK_TL_AXI_LEN           1
#define IO_SUBCTRL_ICG_DIS_PCIE3_CLK_TL_AXI_OFFSET        31
#define IO_SUBCTRL_ICG_DIS_PCIE3_CLK_AP_AXI_LEN           5
#define IO_SUBCTRL_ICG_DIS_PCIE3_CLK_AP_AXI_OFFSET        26
#define IO_SUBCTRL_ICG_DIS_PCIE3_CLK_APB_LEN              2
#define IO_SUBCTRL_ICG_DIS_PCIE3_CLK_APB_OFFSET           24
#define IO_SUBCTRL_ICG_DIS_PCIE3_CLK_CORE_PHY_LANE_LEN    4
#define IO_SUBCTRL_ICG_DIS_PCIE3_CLK_CORE_PHY_LANE_OFFSET 20
#define IO_SUBCTRL_ICG_DIS_PCIE3_CLK_PCS_LOGIC_LEN        4
#define IO_SUBCTRL_ICG_DIS_PCIE3_CLK_PCS_LOGIC_OFFSET     16
#define IO_SUBCTRL_ICG_DIS_PCIE3_CLK_PCS_LOGIC_DIV_LEN    4
#define IO_SUBCTRL_ICG_DIS_PCIE3_CLK_PCS_LOGIC_DIV_OFFSET 12
#define IO_SUBCTRL_ICG_DIS_PCIE3_CLK_PCS_RX_LEN           4
#define IO_SUBCTRL_ICG_DIS_PCIE3_CLK_PCS_RX_OFFSET        8
#define IO_SUBCTRL_ICG_DIS_PCIE3_CLK_PCS_TX_LEN           4
#define IO_SUBCTRL_ICG_DIS_PCIE3_CLK_PCS_TX_OFFSET        4
#define IO_SUBCTRL_ICG_DIS_PCIE3_CLK_PIPE_LANE_LEN        4
#define IO_SUBCTRL_ICG_DIS_PCIE3_CLK_PIPE_LANE_OFFSET     0

#define IO_SUBCTRL_ICG_EN_PCIE3_CLK_CORE_PHY_COMMON_LEN      1
#define IO_SUBCTRL_ICG_EN_PCIE3_CLK_CORE_PHY_COMMON_OFFSET   7
#define IO_SUBCTRL_ICG_EN_PCIE3_CLK_CORE_PHY_PORT_LEN        1
#define IO_SUBCTRL_ICG_EN_PCIE3_CLK_CORE_PHY_PORT_OFFSET     6
#define IO_SUBCTRL_ICG_EN_PCIE3_CLK_CORE_PHY_PORT_DIV_LEN    1
#define IO_SUBCTRL_ICG_EN_PCIE3_CLK_CORE_PHY_PORT_DIV_OFFSET 5
#define IO_SUBCTRL_ICG_EN_PCIE3_CLK_CORE_TL_COMMON_LEN       1
#define IO_SUBCTRL_ICG_EN_PCIE3_CLK_CORE_TL_COMMON_OFFSET    4
#define IO_SUBCTRL_ICG_EN_PCIE3_CLK_CORE_TL_PORT_LEN         1
#define IO_SUBCTRL_ICG_EN_PCIE3_CLK_CORE_TL_PORT_OFFSET      3
#define IO_SUBCTRL_ICG_EN_PCIE3_CLK_CORE_TL_PORT_DIV_LEN     1
#define IO_SUBCTRL_ICG_EN_PCIE3_CLK_CORE_TL_PORT_DIV_OFFSET  2
#define IO_SUBCTRL_ICG_EN_PCIE3_CLK_PCS_APB_LEN              1
#define IO_SUBCTRL_ICG_EN_PCIE3_CLK_PCS_APB_OFFSET           1
#define IO_SUBCTRL_ICG_EN_PCIE3_CLK_PCS_LOGIC_COMMON_LEN     1
#define IO_SUBCTRL_ICG_EN_PCIE3_CLK_PCS_LOGIC_COMMON_OFFSET  0

#define IO_SUBCTRL_ICG_DIS_PCIE3_CLK_CORE_PHY_COMMON_LEN      1
#define IO_SUBCTRL_ICG_DIS_PCIE3_CLK_CORE_PHY_COMMON_OFFSET   7
#define IO_SUBCTRL_ICG_DIS_PCIE3_CLK_CORE_PHY_PORT_LEN        1
#define IO_SUBCTRL_ICG_DIS_PCIE3_CLK_CORE_PHY_PORT_OFFSET     6
#define IO_SUBCTRL_ICG_DIS_PCIE3_CLK_CORE_PHY_PORT_DIV_LEN    1
#define IO_SUBCTRL_ICG_DIS_PCIE3_CLK_CORE_PHY_PORT_DIV_OFFSET 5
#define IO_SUBCTRL_ICG_DIS_PCIE3_CLK_CORE_TL_COMMON_LEN       1
#define IO_SUBCTRL_ICG_DIS_PCIE3_CLK_CORE_TL_COMMON_OFFSET    4
#define IO_SUBCTRL_ICG_DIS_PCIE3_CLK_CORE_TL_PORT_LEN         1
#define IO_SUBCTRL_ICG_DIS_PCIE3_CLK_CORE_TL_PORT_OFFSET      3
#define IO_SUBCTRL_ICG_DIS_PCIE3_CLK_CORE_TL_PORT_DIV_LEN     1
#define IO_SUBCTRL_ICG_DIS_PCIE3_CLK_CORE_TL_PORT_DIV_OFFSET  2
#define IO_SUBCTRL_ICG_DIS_PCIE3_CLK_PCS_APB_LEN              1
#define IO_SUBCTRL_ICG_DIS_PCIE3_CLK_PCS_APB_OFFSET           1
#define IO_SUBCTRL_ICG_DIS_PCIE3_CLK_PCS_LOGIC_COMMON_LEN     1
#define IO_SUBCTRL_ICG_DIS_PCIE3_CLK_PCS_LOGIC_COMMON_OFFSET  0

#define IO_SUBCTRL_ICG_EN_USBC_SYS_LEN    4
#define IO_SUBCTRL_ICG_EN_USBC_SYS_OFFSET 0

#define IO_SUBCTRL_ICG_DIS_USBC_SYS_LEN    4
#define IO_SUBCTRL_ICG_DIS_USBC_SYS_OFFSET 0

#define IO_SUBCTRL_ICG_EN_SATA_OOB_LEN    1
#define IO_SUBCTRL_ICG_EN_SATA_OOB_OFFSET 10
#define IO_SUBCTRL_ICG_EN_SATA_AXI_LEN    1
#define IO_SUBCTRL_ICG_EN_SATA_AXI_OFFSET 9
#define IO_SUBCTRL_ICG_EN_SATA_AHB_LEN    1
#define IO_SUBCTRL_ICG_EN_SATA_AHB_OFFSET 8
#define IO_SUBCTRL_ICG_EN_SATA_RX_LEN     4
#define IO_SUBCTRL_ICG_EN_SATA_RX_OFFSET  4
#define IO_SUBCTRL_ICG_EN_SATA_TX_LEN     4
#define IO_SUBCTRL_ICG_EN_SATA_TX_OFFSET  0

#define IO_SUBCTRL_ICG_DIS_SATA_OOB_LEN    1
#define IO_SUBCTRL_ICG_DIS_SATA_OOB_OFFSET 10
#define IO_SUBCTRL_ICG_DIS_SATA_AXI_LEN    1
#define IO_SUBCTRL_ICG_DIS_SATA_AXI_OFFSET 9
#define IO_SUBCTRL_ICG_DIS_SATA_AHB_LEN    1
#define IO_SUBCTRL_ICG_DIS_SATA_AHB_OFFSET 8
#define IO_SUBCTRL_ICG_DIS_SATA_RX_LEN     4
#define IO_SUBCTRL_ICG_DIS_SATA_RX_OFFSET  4
#define IO_SUBCTRL_ICG_DIS_SATA_TX_LEN     4
#define IO_SUBCTRL_ICG_DIS_SATA_TX_OFFSET  0

#define IO_SUBCTRL_ICG_EN_NIC_RGMII_RX_INV_LEN    2
#define IO_SUBCTRL_ICG_EN_NIC_RGMII_RX_INV_OFFSET 30
#define IO_SUBCTRL_ICG_EN_NIC_RGMII_RX_LEN        2
#define IO_SUBCTRL_ICG_EN_NIC_RGMII_RX_OFFSET     28
#define IO_SUBCTRL_ICG_EN_NIC_RGMII_TX_INV_LEN    2
#define IO_SUBCTRL_ICG_EN_NIC_RGMII_TX_INV_OFFSET 26
#define IO_SUBCTRL_ICG_EN_NIC_RGMII_TX_LEN        2
#define IO_SUBCTRL_ICG_EN_NIC_RGMII_TX_OFFSET     24
#define IO_SUBCTRL_ICG_EN_NIC_XXVGE_RX_SDS_LEN    4
#define IO_SUBCTRL_ICG_EN_NIC_XXVGE_RX_SDS_OFFSET 20
#define IO_SUBCTRL_ICG_EN_NIC_XXVGE_TX_SDS_LEN    4
#define IO_SUBCTRL_ICG_EN_NIC_XXVGE_TX_SDS_OFFSET 16
#define IO_SUBCTRL_ICG_EN_NIC_XXVGE_CORE_LEN      4
#define IO_SUBCTRL_ICG_EN_NIC_XXVGE_CORE_OFFSET   12
#define IO_SUBCTRL_ICG_EN_NIC_XXVGE_CFG_LEN       4
#define IO_SUBCTRL_ICG_EN_NIC_XXVGE_CFG_OFFSET    8
#define IO_SUBCTRL_ICG_EN_NIC_XXVGE_PTP_LEN       4
#define IO_SUBCTRL_ICG_EN_NIC_XXVGE_PTP_OFFSET    4
#define IO_SUBCTRL_ICG_EN_NIC_PTP_LEN             4
#define IO_SUBCTRL_ICG_EN_NIC_PTP_OFFSET          0

#define IO_SUBCTRL_ICG_DIS_NIC_RGMII_RX_INV_LEN    2
#define IO_SUBCTRL_ICG_DIS_NIC_RGMII_RX_INV_OFFSET 30
#define IO_SUBCTRL_ICG_DIS_NIC_RGMII_RX_LEN        2
#define IO_SUBCTRL_ICG_DIS_NIC_RGMII_RX_OFFSET     28
#define IO_SUBCTRL_ICG_DIS_NIC_RGMII_TX_INV_LEN    2
#define IO_SUBCTRL_ICG_DIS_NIC_RGMII_TX_INV_OFFSET 26
#define IO_SUBCTRL_ICG_DIS_NIC_RGMII_TX_LEN        2
#define IO_SUBCTRL_ICG_DIS_NIC_RGMII_TX_OFFSET     24
#define IO_SUBCTRL_ICG_DIS_NIC_XXVGE_RX_SDS_LEN    4
#define IO_SUBCTRL_ICG_DIS_NIC_XXVGE_RX_SDS_OFFSET 20
#define IO_SUBCTRL_ICG_DIS_NIC_XXVGE_TX_SDS_LEN    4
#define IO_SUBCTRL_ICG_DIS_NIC_XXVGE_TX_SDS_OFFSET 16
#define IO_SUBCTRL_ICG_DIS_NIC_XXVGE_CORE_LEN      4
#define IO_SUBCTRL_ICG_DIS_NIC_XXVGE_CORE_OFFSET   12
#define IO_SUBCTRL_ICG_DIS_NIC_XXVGE_CFG_LEN       4
#define IO_SUBCTRL_ICG_DIS_NIC_XXVGE_CFG_OFFSET    8
#define IO_SUBCTRL_ICG_DIS_NIC_XXVGE_PTP_LEN       4
#define IO_SUBCTRL_ICG_DIS_NIC_XXVGE_PTP_OFFSET    4
#define IO_SUBCTRL_ICG_DIS_NIC_PTP_LEN             4
#define IO_SUBCTRL_ICG_DIS_NIC_PTP_OFFSET          0

#define IO_SUBCTRL_ICG_EN_NIC_MAG_APP_LEN    1
#define IO_SUBCTRL_ICG_EN_NIC_MAG_APP_OFFSET 4
#define IO_SUBCTRL_ICG_EN_NIC_MAG_CFG_LEN    1
#define IO_SUBCTRL_ICG_EN_NIC_MAG_CFG_OFFSET 3
#define IO_SUBCTRL_ICG_EN_NIC_SLV_LEN        1
#define IO_SUBCTRL_ICG_EN_NIC_SLV_OFFSET     2
#define IO_SUBCTRL_ICG_EN_NIC_COMMON_LEN     1
#define IO_SUBCTRL_ICG_EN_NIC_COMMON_OFFSET  1
#define IO_SUBCTRL_ICG_EN_NIC_PPE_LEN        1
#define IO_SUBCTRL_ICG_EN_NIC_PPE_OFFSET     0

#define IO_SUBCTRL_ICG_DIS_NIC_MAG_APP_LEN    1
#define IO_SUBCTRL_ICG_DIS_NIC_MAG_APP_OFFSET 4
#define IO_SUBCTRL_ICG_DIS_NIC_MAG_CFG_LEN    1
#define IO_SUBCTRL_ICG_DIS_NIC_MAG_CFG_OFFSET 3
#define IO_SUBCTRL_ICG_DIS_NIC_SLV_LEN        1
#define IO_SUBCTRL_ICG_DIS_NIC_SLV_OFFSET     2
#define IO_SUBCTRL_ICG_DIS_NIC_COMMON_LEN     1
#define IO_SUBCTRL_ICG_DIS_NIC_COMMON_OFFSET  1
#define IO_SUBCTRL_ICG_DIS_NIC_PPE_LEN        1
#define IO_SUBCTRL_ICG_DIS_NIC_PPE_OFFSET     0

#define IO_SUBCTRL_ICG_EN_RGMII_RX_LEN        2
#define IO_SUBCTRL_ICG_EN_RGMII_RX_OFFSET     6
#define IO_SUBCTRL_ICG_EN_RGMII_RX_INV_LEN    2
#define IO_SUBCTRL_ICG_EN_RGMII_RX_INV_OFFSET 4
#define IO_SUBCTRL_ICG_EN_RGMII_TX_LEN        2
#define IO_SUBCTRL_ICG_EN_RGMII_TX_OFFSET     2
#define IO_SUBCTRL_ICG_EN_RGMII_TX_INV_LEN    2
#define IO_SUBCTRL_ICG_EN_RGMII_TX_INV_OFFSET 0

#define IO_SUBCTRL_ICG_DIS_RGMII_RX_LEN        2
#define IO_SUBCTRL_ICG_DIS_RGMII_RX_OFFSET     6
#define IO_SUBCTRL_ICG_DIS_RGMII_RX_INV_LEN    2
#define IO_SUBCTRL_ICG_DIS_RGMII_RX_INV_OFFSET 4
#define IO_SUBCTRL_ICG_DIS_RGMII_TX_LEN        2
#define IO_SUBCTRL_ICG_DIS_RGMII_TX_OFFSET     2
#define IO_SUBCTRL_ICG_DIS_RGMII_TX_INV_LEN    2
#define IO_SUBCTRL_ICG_DIS_RGMII_TX_INV_OFFSET 0

#define IO_SUBCTRL_ICG_EN_HPM_LEN    1
#define IO_SUBCTRL_ICG_EN_HPM_OFFSET 0

#define IO_SUBCTRL_ICG_DIS_HPM_LEN    1
#define IO_SUBCTRL_ICG_DIS_HPM_OFFSET 0

#define IO_SUBCTRL_ICG_EN_SENSOR_SAMP_LEN    1
#define IO_SUBCTRL_ICG_EN_SENSOR_SAMP_OFFSET 1
#define IO_SUBCTRL_ICG_EN_SENSOR_LEN         1
#define IO_SUBCTRL_ICG_EN_SENSOR_OFFSET      0

#define IO_SUBCTRL_ICG_DIS_SENSOR_SAMP_LEN    1
#define IO_SUBCTRL_ICG_DIS_SENSOR_SAMP_OFFSET 1
#define IO_SUBCTRL_ICG_DIS_SENSOR_LEN         1
#define IO_SUBCTRL_ICG_DIS_SENSOR_OFFSET      0

#define IO_SUBCTRL_ICG_EN_HILINK1_SRAM1_LEN    1
#define IO_SUBCTRL_ICG_EN_HILINK1_SRAM1_OFFSET 3
#define IO_SUBCTRL_ICG_EN_HILINK1_SRAM0_LEN    1
#define IO_SUBCTRL_ICG_EN_HILINK1_SRAM0_OFFSET 2
#define IO_SUBCTRL_ICG_EN_HILINK0_SRAM1_LEN    1
#define IO_SUBCTRL_ICG_EN_HILINK0_SRAM1_OFFSET 1
#define IO_SUBCTRL_ICG_EN_HILINK0_SRAM0_LEN    1
#define IO_SUBCTRL_ICG_EN_HILINK0_SRAM0_OFFSET 0

#define IO_SUBCTRL_ICG_DIS_HILINK1_SRAM1_LEN    1
#define IO_SUBCTRL_ICG_DIS_HILINK1_SRAM1_OFFSET 3
#define IO_SUBCTRL_ICG_DIS_HILINK1_SRAM0_LEN    1
#define IO_SUBCTRL_ICG_DIS_HILINK1_SRAM0_OFFSET 2
#define IO_SUBCTRL_ICG_DIS_HILINK0_SRAM1_LEN    1
#define IO_SUBCTRL_ICG_DIS_HILINK0_SRAM1_OFFSET 1
#define IO_SUBCTRL_ICG_DIS_HILINK0_SRAM0_LEN    1
#define IO_SUBCTRL_ICG_DIS_HILINK0_SRAM0_OFFSET 0

#define IO_SUBCTRL_ICG_EN_BCBIST0_LEN    1
#define IO_SUBCTRL_ICG_EN_BCBIST0_OFFSET 0

#define IO_SUBCTRL_ICG_DIS_BCBIST0_LEN    1
#define IO_SUBCTRL_ICG_DIS_BCBIST0_OFFSET 0

#define IO_SUBCTRL_SRST_REQ_GPIO_LEN    2
#define IO_SUBCTRL_SRST_REQ_GPIO_OFFSET 0

#define IO_SUBCTRL_SRST_DREQ_GPIO_LEN    2
#define IO_SUBCTRL_SRST_DREQ_GPIO_OFFSET 0

#define IO_SUBCTRL_SRST_REQ_APB_IO_MUX_LEN    1
#define IO_SUBCTRL_SRST_REQ_APB_IO_MUX_OFFSET 0

#define IO_SUBCTRL_SRST_DREQ_APB_IO_MUX_LEN    1
#define IO_SUBCTRL_SRST_DREQ_APB_IO_MUX_OFFSET 0

#define IO_SUBCTRL_SRST_REQ_MDIO_LEN    2
#define IO_SUBCTRL_SRST_REQ_MDIO_OFFSET 0

#define IO_SUBCTRL_SRST_DREQ_MDIO_LEN    2
#define IO_SUBCTRL_SRST_DREQ_MDIO_OFFSET 0

#define IO_SUBCTRL_SRST_REQ_HILINK0_PMA_RX_LEN    4
#define IO_SUBCTRL_SRST_REQ_HILINK0_PMA_RX_OFFSET 4
#define IO_SUBCTRL_SRST_REQ_HILINK0_PMA_TX_LEN    4
#define IO_SUBCTRL_SRST_REQ_HILINK0_PMA_TX_OFFSET 0

#define IO_SUBCTRL_SRST_DREQ_HILINK0_PMA_RX_LEN    4
#define IO_SUBCTRL_SRST_DREQ_HILINK0_PMA_RX_OFFSET 4
#define IO_SUBCTRL_SRST_DREQ_HILINK0_PMA_TX_LEN    4
#define IO_SUBCTRL_SRST_DREQ_HILINK0_PMA_TX_OFFSET 0

#define IO_SUBCTRL_SRST_REQ_HILINK1_PMA_RX_LEN    4
#define IO_SUBCTRL_SRST_REQ_HILINK1_PMA_RX_OFFSET 4
#define IO_SUBCTRL_SRST_REQ_HILINK1_PMA_TX_LEN    4
#define IO_SUBCTRL_SRST_REQ_HILINK1_PMA_TX_OFFSET 0

#define IO_SUBCTRL_SRST_DREQ_HILINK1_PMA_RX_LEN    4
#define IO_SUBCTRL_SRST_DREQ_HILINK1_PMA_RX_OFFSET 4
#define IO_SUBCTRL_SRST_DREQ_HILINK1_PMA_TX_LEN    4
#define IO_SUBCTRL_SRST_DREQ_HILINK1_PMA_TX_OFFSET 0

#define IO_SUBCTRL_SRST_REQ_SDS_SDPI_LEN    2
#define IO_SUBCTRL_SRST_REQ_SDS_SDPI_OFFSET 4
#define IO_SUBCTRL_SRST_REQ_ADAP_LEN        4
#define IO_SUBCTRL_SRST_REQ_ADAP_OFFSET     0

#define IO_SUBCTRL_SRST_DREQ_SDS_SDPI_LEN    2
#define IO_SUBCTRL_SRST_DREQ_SDS_SDPI_OFFSET 4
#define IO_SUBCTRL_SRST_DREQ_ADAP_LEN        4
#define IO_SUBCTRL_SRST_DREQ_ADAP_OFFSET     0

#define IO_SUBCTRL_SRST_REQ_USBC_SYS_LEN        4
#define IO_SUBCTRL_SRST_REQ_USBC_SYS_OFFSET     8
#define IO_SUBCTRL_SRST_REQ_USBC_SUSPEND_LEN    4
#define IO_SUBCTRL_SRST_REQ_USBC_SUSPEND_OFFSET 4
#define IO_SUBCTRL_SRST_REQ_USBC_REF_LEN        4
#define IO_SUBCTRL_SRST_REQ_USBC_REF_OFFSET     0

#define IO_SUBCTRL_SRST_DREQ_USBC_SYS_LEN        4
#define IO_SUBCTRL_SRST_DREQ_USBC_SYS_OFFSET     8
#define IO_SUBCTRL_SRST_DREQ_USBC_SUSPEND_LEN    4
#define IO_SUBCTRL_SRST_DREQ_USBC_SUSPEND_OFFSET 4
#define IO_SUBCTRL_SRST_DREQ_USBC_REF_LEN        4
#define IO_SUBCTRL_SRST_DREQ_USBC_REF_OFFSET     0

#define IO_SUBCTRL_SRST_REQ_PHY_LEN    3
#define IO_SUBCTRL_SRST_REQ_PHY_OFFSET 0

#define IO_SUBCTRL_SRST_DREQ_PHY_LEN    3
#define IO_SUBCTRL_SRST_DREQ_PHY_OFFSET 0

#define IO_SUBCTRL_SRST_REQ_SATA_OOB_LEN    1
#define IO_SUBCTRL_SRST_REQ_SATA_OOB_OFFSET 10
#define IO_SUBCTRL_SRST_REQ_SATA_AXI_LEN    1
#define IO_SUBCTRL_SRST_REQ_SATA_AXI_OFFSET 9
#define IO_SUBCTRL_SRST_REQ_SATA_AHB_LEN    1
#define IO_SUBCTRL_SRST_REQ_SATA_AHB_OFFSET 8
#define IO_SUBCTRL_SRST_REQ_SATA_RX_LEN     4
#define IO_SUBCTRL_SRST_REQ_SATA_RX_OFFSET  4
#define IO_SUBCTRL_SRST_REQ_SATA_TX_LEN     4
#define IO_SUBCTRL_SRST_REQ_SATA_TX_OFFSET  0

#define IO_SUBCTRL_SRST_DREQ_SATA_OOB_LEN    1
#define IO_SUBCTRL_SRST_DREQ_SATA_OOB_OFFSET 10
#define IO_SUBCTRL_SRST_DREQ_SATA_AXI_LEN    1
#define IO_SUBCTRL_SRST_DREQ_SATA_AXI_OFFSET 9
#define IO_SUBCTRL_SRST_DREQ_SATA_AHB_LEN    1
#define IO_SUBCTRL_SRST_DREQ_SATA_AHB_OFFSET 8
#define IO_SUBCTRL_SRST_DREQ_SATA_RX_LEN     4
#define IO_SUBCTRL_SRST_DREQ_SATA_RX_OFFSET  4
#define IO_SUBCTRL_SRST_DREQ_SATA_TX_LEN     4
#define IO_SUBCTRL_SRST_DREQ_SATA_TX_OFFSET  0

#define IO_SUBCTRL_SRST_REQ_NIC_RGMII_RX_INV_LEN       2
#define IO_SUBCTRL_SRST_REQ_NIC_RGMII_RX_INV_OFFSET    30
#define IO_SUBCTRL_SRST_REQ_NIC_RGMII_RX_LEN           2
#define IO_SUBCTRL_SRST_REQ_NIC_RGMII_RX_OFFSET        28
#define IO_SUBCTRL_SRST_REQ_NIC_RGMII_TX_INV_LEN       2
#define IO_SUBCTRL_SRST_REQ_NIC_RGMII_TX_INV_OFFSET    26
#define IO_SUBCTRL_SRST_REQ_NIC_RGMII_TX_LEN           2
#define IO_SUBCTRL_SRST_REQ_NIC_RGMII_TX_OFFSET        24
#define IO_SUBCTRL_SRST_REQ_NIC_PTP_LEN                4
#define IO_SUBCTRL_SRST_REQ_NIC_PTP_OFFSET             20
#define IO_SUBCTRL_SRST_REQ_NIC_XXVGE_CORE_SYNC_LEN    4
#define IO_SUBCTRL_SRST_REQ_NIC_XXVGE_CORE_SYNC_OFFSET 16
#define IO_SUBCTRL_SRST_REQ_NIC_XXVGE_CORE_LEN         4
#define IO_SUBCTRL_SRST_REQ_NIC_XXVGE_CORE_OFFSET      12
#define IO_SUBCTRL_SRST_REQ_NIC_XXVGE_CFG_LEN          4
#define IO_SUBCTRL_SRST_REQ_NIC_XXVGE_CFG_OFFSET       8
#define IO_SUBCTRL_SRST_REQ_NIC_XXVGE_PTP_SYNC_LEN     4
#define IO_SUBCTRL_SRST_REQ_NIC_XXVGE_PTP_SYNC_OFFSET  4
#define IO_SUBCTRL_SRST_REQ_NIC_XXVGE_T_LEN            4
#define IO_SUBCTRL_SRST_REQ_NIC_XXVGE_T_OFFSET         0

#define IO_SUBCTRL_SRST_DREQ_NIC_RGMII_RX_INV_LEN       2
#define IO_SUBCTRL_SRST_DREQ_NIC_RGMII_RX_INV_OFFSET    30
#define IO_SUBCTRL_SRST_DREQ_NIC_RGMII_RX_LEN           2
#define IO_SUBCTRL_SRST_DREQ_NIC_RGMII_RX_OFFSET        28
#define IO_SUBCTRL_SRST_DREQ_NIC_RGMII_TX_INV_LEN       2
#define IO_SUBCTRL_SRST_DREQ_NIC_RGMII_TX_INV_OFFSET    26
#define IO_SUBCTRL_SRST_DREQ_NIC_RGMII_TX_LEN           2
#define IO_SUBCTRL_SRST_DREQ_NIC_RGMII_TX_OFFSET        24
#define IO_SUBCTRL_SRST_DREQ_NIC_PTP_LEN                4
#define IO_SUBCTRL_SRST_DREQ_NIC_PTP_OFFSET             20
#define IO_SUBCTRL_SRST_DREQ_NIC_XXVGE_CORE_SYNC_LEN    4
#define IO_SUBCTRL_SRST_DREQ_NIC_XXVGE_CORE_SYNC_OFFSET 16
#define IO_SUBCTRL_SRST_DREQ_NIC_XXVGE_CORE_LEN         4
#define IO_SUBCTRL_SRST_DREQ_NIC_XXVGE_CORE_OFFSET      12
#define IO_SUBCTRL_SRST_DREQ_NIC_XXVGE_CFG_LEN          4
#define IO_SUBCTRL_SRST_DREQ_NIC_XXVGE_CFG_OFFSET       8
#define IO_SUBCTRL_SRST_DREQ_NIC_XXVGE_PTP_SYNC_LEN     4
#define IO_SUBCTRL_SRST_DREQ_NIC_XXVGE_PTP_SYNC_OFFSET  4
#define IO_SUBCTRL_SRST_DREQ_NIC_XXVGE_T_LEN            4
#define IO_SUBCTRL_SRST_DREQ_NIC_XXVGE_T_OFFSET         0

#define IO_SUBCTRL_SRST_REQ_NIC_MAG_APP_SYNC_LEN    1
#define IO_SUBCTRL_SRST_REQ_NIC_MAG_APP_SYNC_OFFSET 7
#define IO_SUBCTRL_SRST_REQ_NIC_MAG_APP_LEN         1
#define IO_SUBCTRL_SRST_REQ_NIC_MAG_APP_OFFSET      6
#define IO_SUBCTRL_SRST_REQ_NIC_MAG_CFG_LEN         1
#define IO_SUBCTRL_SRST_REQ_NIC_MAG_CFG_OFFSET      5
#define IO_SUBCTRL_SRST_REQ_NIC_SLV_LEN             1
#define IO_SUBCTRL_SRST_REQ_NIC_SLV_OFFSET          4
#define IO_SUBCTRL_SRST_REQ_NIC_COMMON_REG_LEN      1
#define IO_SUBCTRL_SRST_REQ_NIC_COMMON_REG_OFFSET   3
#define IO_SUBCTRL_SRST_REQ_NIC_COMMON_LEN          1
#define IO_SUBCTRL_SRST_REQ_NIC_COMMON_OFFSET       2
#define IO_SUBCTRL_SRST_REQ_NIC_PPE_REG_LEN         1
#define IO_SUBCTRL_SRST_REQ_NIC_PPE_REG_OFFSET      1
#define IO_SUBCTRL_SRST_REQ_NIC_PPE_LEN             1
#define IO_SUBCTRL_SRST_REQ_NIC_PPE_OFFSET          0

#define IO_SUBCTRL_SRST_DREQ_NIC_MAG_APP_SYNC_LEN    1
#define IO_SUBCTRL_SRST_DREQ_NIC_MAG_APP_SYNC_OFFSET 7
#define IO_SUBCTRL_SRST_DREQ_NIC_MAG_APP_LEN         1
#define IO_SUBCTRL_SRST_DREQ_NIC_MAG_APP_OFFSET      6
#define IO_SUBCTRL_SRST_DREQ_NIC_MAG_CFG_LEN         1
#define IO_SUBCTRL_SRST_DREQ_NIC_MAG_CFG_OFFSET      5
#define IO_SUBCTRL_SRST_DREQ_NIC_SLV_LEN             1
#define IO_SUBCTRL_SRST_DREQ_NIC_SLV_OFFSET          4
#define IO_SUBCTRL_SRST_DREQ_NIC_COMMON_REG_LEN      1
#define IO_SUBCTRL_SRST_DREQ_NIC_COMMON_REG_OFFSET   3
#define IO_SUBCTRL_SRST_DREQ_NIC_COMMON_LEN          1
#define IO_SUBCTRL_SRST_DREQ_NIC_COMMON_OFFSET       2
#define IO_SUBCTRL_SRST_DREQ_NIC_PPE_REG_LEN         1
#define IO_SUBCTRL_SRST_DREQ_NIC_PPE_REG_OFFSET      1
#define IO_SUBCTRL_SRST_DREQ_NIC_PPE_LEN             1
#define IO_SUBCTRL_SRST_DREQ_NIC_PPE_OFFSET          0

#define IO_SUBCTRL_SRST_REQ_PCIE0_LEN              1
#define IO_SUBCTRL_SRST_REQ_PCIE0_OFFSET           22
#define IO_SUBCTRL_SRST_REQ_PCIE0_AP_AXI_LEN       1
#define IO_SUBCTRL_SRST_REQ_PCIE0_AP_AXI_OFFSET    21
#define IO_SUBCTRL_SRST_REQ_PCIE0_APB_LEN          1
#define IO_SUBCTRL_SRST_REQ_PCIE0_APB_OFFSET       20
#define IO_SUBCTRL_SRST_REQ_PCIE0_CORE_PHY_LEN     1
#define IO_SUBCTRL_SRST_REQ_PCIE0_CORE_PHY_OFFSET  19
#define IO_SUBCTRL_SRST_REQ_PCIE0_CORE_TL_LEN      1
#define IO_SUBCTRL_SRST_REQ_PCIE0_CORE_TL_OFFSET   18
#define IO_SUBCTRL_SRST_REQ_PCIE0_PCS_LOGIC_LEN    1
#define IO_SUBCTRL_SRST_REQ_PCIE0_PCS_LOGIC_OFFSET 17
#define IO_SUBCTRL_SRST_REQ_PCIE0_TL_AXI_LEN       1
#define IO_SUBCTRL_SRST_REQ_PCIE0_TL_AXI_OFFSET    16
#define IO_SUBCTRL_SRST_REQ_PCIE0_PCS_RX_LEN       4
#define IO_SUBCTRL_SRST_REQ_PCIE0_PCS_RX_OFFSET    12
#define IO_SUBCTRL_SRST_REQ_PCIE0_PCS_TX_LEN       4
#define IO_SUBCTRL_SRST_REQ_PCIE0_PCS_TX_OFFSET    8
#define IO_SUBCTRL_SRST_REQ_PCIE0_PIPE_LEN         4
#define IO_SUBCTRL_SRST_REQ_PCIE0_PIPE_OFFSET      4
#define IO_SUBCTRL_SRST_REQ_PCIE0_PIPE_LANE_LEN    4
#define IO_SUBCTRL_SRST_REQ_PCIE0_PIPE_LANE_OFFSET 0

#define IO_SUBCTRL_SRST_DREQ_PCIE0_LEN              1
#define IO_SUBCTRL_SRST_DREQ_PCIE0_OFFSET           22
#define IO_SUBCTRL_SRST_DREQ_PCIE0_AP_AXI_LEN       1
#define IO_SUBCTRL_SRST_DREQ_PCIE0_AP_AXI_OFFSET    21
#define IO_SUBCTRL_SRST_DREQ_PCIE0_APB_LEN          1
#define IO_SUBCTRL_SRST_DREQ_PCIE0_APB_OFFSET       20
#define IO_SUBCTRL_SRST_DREQ_PCIE0_CORE_PHY_LEN     1
#define IO_SUBCTRL_SRST_DREQ_PCIE0_CORE_PHY_OFFSET  19
#define IO_SUBCTRL_SRST_DREQ_PCIE0_CORE_TL_LEN      1
#define IO_SUBCTRL_SRST_DREQ_PCIE0_CORE_TL_OFFSET   18
#define IO_SUBCTRL_SRST_DREQ_PCIE0_PCS_LOGIC_LEN    1
#define IO_SUBCTRL_SRST_DREQ_PCIE0_PCS_LOGIC_OFFSET 17
#define IO_SUBCTRL_SRST_DREQ_PCIE0_TL_AXI_LEN       1
#define IO_SUBCTRL_SRST_DREQ_PCIE0_TL_AXI_OFFSET    16
#define IO_SUBCTRL_SRST_DREQ_PCIE0_PCS_RX_LEN       4
#define IO_SUBCTRL_SRST_DREQ_PCIE0_PCS_RX_OFFSET    12
#define IO_SUBCTRL_SRST_DREQ_PCIE0_PCS_TX_LEN       4
#define IO_SUBCTRL_SRST_DREQ_PCIE0_PCS_TX_OFFSET    8
#define IO_SUBCTRL_SRST_DREQ_PCIE0_PIPE_LEN         4
#define IO_SUBCTRL_SRST_DREQ_PCIE0_PIPE_OFFSET      4
#define IO_SUBCTRL_SRST_DREQ_PCIE0_PIPE_LANE_LEN    4
#define IO_SUBCTRL_SRST_DREQ_PCIE0_PIPE_LANE_OFFSET 0

#define IO_SUBCTRL_SRST_REQ_PCIE1_LEN              1
#define IO_SUBCTRL_SRST_REQ_PCIE1_OFFSET           22
#define IO_SUBCTRL_SRST_REQ_PCIE1_AP_AXI_LEN       1
#define IO_SUBCTRL_SRST_REQ_PCIE1_AP_AXI_OFFSET    21
#define IO_SUBCTRL_SRST_REQ_PCIE1_APB_LEN          1
#define IO_SUBCTRL_SRST_REQ_PCIE1_APB_OFFSET       20
#define IO_SUBCTRL_SRST_REQ_PCIE1_CORE_PHY_LEN     1
#define IO_SUBCTRL_SRST_REQ_PCIE1_CORE_PHY_OFFSET  19
#define IO_SUBCTRL_SRST_REQ_PCIE1_CORE_TL_LEN      1
#define IO_SUBCTRL_SRST_REQ_PCIE1_CORE_TL_OFFSET   18
#define IO_SUBCTRL_SRST_REQ_PCIE1_PCS_LOGIC_LEN    1
#define IO_SUBCTRL_SRST_REQ_PCIE1_PCS_LOGIC_OFFSET 17
#define IO_SUBCTRL_SRST_REQ_PCIE1_TL_AXI_LEN       1
#define IO_SUBCTRL_SRST_REQ_PCIE1_TL_AXI_OFFSET    16
#define IO_SUBCTRL_SRST_REQ_PCIE1_PCS_RX_LEN       4
#define IO_SUBCTRL_SRST_REQ_PCIE1_PCS_RX_OFFSET    12
#define IO_SUBCTRL_SRST_REQ_PCIE1_PCS_TX_LEN       4
#define IO_SUBCTRL_SRST_REQ_PCIE1_PCS_TX_OFFSET    8
#define IO_SUBCTRL_SRST_REQ_PCIE1_PIPE_LEN         4
#define IO_SUBCTRL_SRST_REQ_PCIE1_PIPE_OFFSET      4
#define IO_SUBCTRL_SRST_REQ_PCIE1_PIPE_LANE_LEN    4
#define IO_SUBCTRL_SRST_REQ_PCIE1_PIPE_LANE_OFFSET 0

#define IO_SUBCTRL_SRST_DREQ_PCIE1_LEN              1
#define IO_SUBCTRL_SRST_DREQ_PCIE1_OFFSET           22
#define IO_SUBCTRL_SRST_DREQ_PCIE1_AP_AXI_LEN       1
#define IO_SUBCTRL_SRST_DREQ_PCIE1_AP_AXI_OFFSET    21
#define IO_SUBCTRL_SRST_DREQ_PCIE1_APB_LEN          1
#define IO_SUBCTRL_SRST_DREQ_PCIE1_APB_OFFSET       20
#define IO_SUBCTRL_SRST_DREQ_PCIE1_CORE_PHY_LEN     1
#define IO_SUBCTRL_SRST_DREQ_PCIE1_CORE_PHY_OFFSET  19
#define IO_SUBCTRL_SRST_DREQ_PCIE1_CORE_TL_LEN      1
#define IO_SUBCTRL_SRST_DREQ_PCIE1_CORE_TL_OFFSET   18
#define IO_SUBCTRL_SRST_DREQ_PCIE1_PCS_LOGIC_LEN    1
#define IO_SUBCTRL_SRST_DREQ_PCIE1_PCS_LOGIC_OFFSET 17
#define IO_SUBCTRL_SRST_DREQ_PCIE1_TL_AXI_LEN       1
#define IO_SUBCTRL_SRST_DREQ_PCIE1_TL_AXI_OFFSET    16
#define IO_SUBCTRL_SRST_DREQ_PCIE1_PCS_RX_LEN       4
#define IO_SUBCTRL_SRST_DREQ_PCIE1_PCS_RX_OFFSET    12
#define IO_SUBCTRL_SRST_DREQ_PCIE1_PCS_TX_LEN       4
#define IO_SUBCTRL_SRST_DREQ_PCIE1_PCS_TX_OFFSET    8
#define IO_SUBCTRL_SRST_DREQ_PCIE1_PIPE_LEN         4
#define IO_SUBCTRL_SRST_DREQ_PCIE1_PIPE_OFFSET      4
#define IO_SUBCTRL_SRST_DREQ_PCIE1_PIPE_LANE_LEN    4
#define IO_SUBCTRL_SRST_DREQ_PCIE1_PIPE_LANE_OFFSET 0

#define IO_SUBCTRL_SRST_REQ_PCIE2_LEN              1
#define IO_SUBCTRL_SRST_REQ_PCIE2_OFFSET           22
#define IO_SUBCTRL_SRST_REQ_PCIE2_AP_AXI_LEN       1
#define IO_SUBCTRL_SRST_REQ_PCIE2_AP_AXI_OFFSET    21
#define IO_SUBCTRL_SRST_REQ_PCIE2_APB_LEN          1
#define IO_SUBCTRL_SRST_REQ_PCIE2_APB_OFFSET       20
#define IO_SUBCTRL_SRST_REQ_PCIE2_CORE_PHY_LEN     1
#define IO_SUBCTRL_SRST_REQ_PCIE2_CORE_PHY_OFFSET  19
#define IO_SUBCTRL_SRST_REQ_PCIE2_CORE_TL_LEN      1
#define IO_SUBCTRL_SRST_REQ_PCIE2_CORE_TL_OFFSET   18
#define IO_SUBCTRL_SRST_REQ_PCIE2_PCS_LOGIC_LEN    1
#define IO_SUBCTRL_SRST_REQ_PCIE2_PCS_LOGIC_OFFSET 17
#define IO_SUBCTRL_SRST_REQ_PCIE2_TL_AXI_LEN       1
#define IO_SUBCTRL_SRST_REQ_PCIE2_TL_AXI_OFFSET    16
#define IO_SUBCTRL_SRST_REQ_PCIE2_PCS_RX_LEN       4
#define IO_SUBCTRL_SRST_REQ_PCIE2_PCS_RX_OFFSET    12
#define IO_SUBCTRL_SRST_REQ_PCIE2_PCS_TX_LEN       4
#define IO_SUBCTRL_SRST_REQ_PCIE2_PCS_TX_OFFSET    8
#define IO_SUBCTRL_SRST_REQ_PCIE2_PIPE_LEN         4
#define IO_SUBCTRL_SRST_REQ_PCIE2_PIPE_OFFSET      4
#define IO_SUBCTRL_SRST_REQ_PCIE2_PIPE_LANE_LEN    4
#define IO_SUBCTRL_SRST_REQ_PCIE2_PIPE_LANE_OFFSET 0

#define IO_SUBCTRL_SRST_DREQ_PCIE2_LEN              1
#define IO_SUBCTRL_SRST_DREQ_PCIE2_OFFSET           22
#define IO_SUBCTRL_SRST_DREQ_PCIE2_AP_AXI_LEN       1
#define IO_SUBCTRL_SRST_DREQ_PCIE2_AP_AXI_OFFSET    21
#define IO_SUBCTRL_SRST_DREQ_PCIE2_APB_LEN          1
#define IO_SUBCTRL_SRST_DREQ_PCIE2_APB_OFFSET       20
#define IO_SUBCTRL_SRST_DREQ_PCIE2_CORE_PHY_LEN     1
#define IO_SUBCTRL_SRST_DREQ_PCIE2_CORE_PHY_OFFSET  19
#define IO_SUBCTRL_SRST_DREQ_PCIE2_CORE_TL_LEN      1
#define IO_SUBCTRL_SRST_DREQ_PCIE2_CORE_TL_OFFSET   18
#define IO_SUBCTRL_SRST_DREQ_PCIE2_PCS_LOGIC_LEN    1
#define IO_SUBCTRL_SRST_DREQ_PCIE2_PCS_LOGIC_OFFSET 17
#define IO_SUBCTRL_SRST_DREQ_PCIE2_TL_AXI_LEN       1
#define IO_SUBCTRL_SRST_DREQ_PCIE2_TL_AXI_OFFSET    16
#define IO_SUBCTRL_SRST_DREQ_PCIE2_PCS_RX_LEN       4
#define IO_SUBCTRL_SRST_DREQ_PCIE2_PCS_RX_OFFSET    12
#define IO_SUBCTRL_SRST_DREQ_PCIE2_PCS_TX_LEN       4
#define IO_SUBCTRL_SRST_DREQ_PCIE2_PCS_TX_OFFSET    8
#define IO_SUBCTRL_SRST_DREQ_PCIE2_PIPE_LEN         4
#define IO_SUBCTRL_SRST_DREQ_PCIE2_PIPE_OFFSET      4
#define IO_SUBCTRL_SRST_DREQ_PCIE2_PIPE_LANE_LEN    4
#define IO_SUBCTRL_SRST_DREQ_PCIE2_PIPE_LANE_OFFSET 0

#define IO_SUBCTRL_SRST_REQ_PCIE3_LEN              1
#define IO_SUBCTRL_SRST_REQ_PCIE3_OFFSET           22
#define IO_SUBCTRL_SRST_REQ_PCIE3_AP_AXI_LEN       1
#define IO_SUBCTRL_SRST_REQ_PCIE3_AP_AXI_OFFSET    21
#define IO_SUBCTRL_SRST_REQ_PCIE3_APB_LEN          1
#define IO_SUBCTRL_SRST_REQ_PCIE3_APB_OFFSET       20
#define IO_SUBCTRL_SRST_REQ_PCIE3_CORE_PHY_LEN     1
#define IO_SUBCTRL_SRST_REQ_PCIE3_CORE_PHY_OFFSET  19
#define IO_SUBCTRL_SRST_REQ_PCIE3_CORE_TL_LEN      1
#define IO_SUBCTRL_SRST_REQ_PCIE3_CORE_TL_OFFSET   18
#define IO_SUBCTRL_SRST_REQ_PCIE3_PCS_LOGIC_LEN    1
#define IO_SUBCTRL_SRST_REQ_PCIE3_PCS_LOGIC_OFFSET 17
#define IO_SUBCTRL_SRST_REQ_PCIE3_TL_AXI_LEN       1
#define IO_SUBCTRL_SRST_REQ_PCIE3_TL_AXI_OFFSET    16
#define IO_SUBCTRL_SRST_REQ_PCIE3_PCS_RX_LEN       4
#define IO_SUBCTRL_SRST_REQ_PCIE3_PCS_RX_OFFSET    12
#define IO_SUBCTRL_SRST_REQ_PCIE3_PCS_TX_LEN       4
#define IO_SUBCTRL_SRST_REQ_PCIE3_PCS_TX_OFFSET    8
#define IO_SUBCTRL_SRST_REQ_PCIE3_PIPE_LEN         4
#define IO_SUBCTRL_SRST_REQ_PCIE3_PIPE_OFFSET      4
#define IO_SUBCTRL_SRST_REQ_PCIE3_PIPE_LANE_LEN    4
#define IO_SUBCTRL_SRST_REQ_PCIE3_PIPE_LANE_OFFSET 0

#define IO_SUBCTRL_SRST_DREQ_PCIE3_LEN              1
#define IO_SUBCTRL_SRST_DREQ_PCIE3_OFFSET           22
#define IO_SUBCTRL_SRST_DREQ_PCIE3_AP_AXI_LEN       1
#define IO_SUBCTRL_SRST_DREQ_PCIE3_AP_AXI_OFFSET    21
#define IO_SUBCTRL_SRST_DREQ_PCIE3_APB_LEN          1
#define IO_SUBCTRL_SRST_DREQ_PCIE3_APB_OFFSET       20
#define IO_SUBCTRL_SRST_DREQ_PCIE3_CORE_PHY_LEN     1
#define IO_SUBCTRL_SRST_DREQ_PCIE3_CORE_PHY_OFFSET  19
#define IO_SUBCTRL_SRST_DREQ_PCIE3_CORE_TL_LEN      1
#define IO_SUBCTRL_SRST_DREQ_PCIE3_CORE_TL_OFFSET   18
#define IO_SUBCTRL_SRST_DREQ_PCIE3_PCS_LOGIC_LEN    1
#define IO_SUBCTRL_SRST_DREQ_PCIE3_PCS_LOGIC_OFFSET 17
#define IO_SUBCTRL_SRST_DREQ_PCIE3_TL_AXI_LEN       1
#define IO_SUBCTRL_SRST_DREQ_PCIE3_TL_AXI_OFFSET    16
#define IO_SUBCTRL_SRST_DREQ_PCIE3_PCS_RX_LEN       4
#define IO_SUBCTRL_SRST_DREQ_PCIE3_PCS_RX_OFFSET    12
#define IO_SUBCTRL_SRST_DREQ_PCIE3_PCS_TX_LEN       4
#define IO_SUBCTRL_SRST_DREQ_PCIE3_PCS_TX_OFFSET    8
#define IO_SUBCTRL_SRST_DREQ_PCIE3_PIPE_LEN         4
#define IO_SUBCTRL_SRST_DREQ_PCIE3_PIPE_OFFSET      4
#define IO_SUBCTRL_SRST_DREQ_PCIE3_PIPE_LANE_LEN    4
#define IO_SUBCTRL_SRST_DREQ_PCIE3_PIPE_LANE_OFFSET 0

#define IO_SUBCTRL_SRST_REQ_RGMII_RX_LEN        2
#define IO_SUBCTRL_SRST_REQ_RGMII_RX_OFFSET     6
#define IO_SUBCTRL_SRST_REQ_RGMII_RX_INV_LEN    2
#define IO_SUBCTRL_SRST_REQ_RGMII_RX_INV_OFFSET 4
#define IO_SUBCTRL_SRST_REQ_RGMII_TX_LEN        2
#define IO_SUBCTRL_SRST_REQ_RGMII_TX_OFFSET     2
#define IO_SUBCTRL_SRST_REQ_RGMII_TX_INV_LEN    2
#define IO_SUBCTRL_SRST_REQ_RGMII_TX_INV_OFFSET 0

#define IO_SUBCTRL_SRST_DREQ_RGMII_RX_LEN        2
#define IO_SUBCTRL_SRST_DREQ_RGMII_RX_OFFSET     6
#define IO_SUBCTRL_SRST_DREQ_RGMII_RX_INV_LEN    2
#define IO_SUBCTRL_SRST_DREQ_RGMII_RX_INV_OFFSET 4
#define IO_SUBCTRL_SRST_DREQ_RGMII_TX_LEN        2
#define IO_SUBCTRL_SRST_DREQ_RGMII_TX_OFFSET     2
#define IO_SUBCTRL_SRST_DREQ_RGMII_TX_INV_LEN    2
#define IO_SUBCTRL_SRST_DREQ_RGMII_TX_INV_OFFSET 0

#define IO_SUBCTRL_SRST_REQ_HPM_LEN    1
#define IO_SUBCTRL_SRST_REQ_HPM_OFFSET 0

#define IO_SUBCTRL_SRST_DREQ_HPM_LEN    1
#define IO_SUBCTRL_SRST_DREQ_HPM_OFFSET 0

#define IO_SUBCTRL_SRST_REQ_SENSOR_SAMP_LEN    1
#define IO_SUBCTRL_SRST_REQ_SENSOR_SAMP_OFFSET 0

#define IO_SUBCTRL_SRST_DREQ_SENSOR_SAMP_LEN    1
#define IO_SUBCTRL_SRST_DREQ_SENSOR_SAMP_OFFSET 0

#define IO_SUBCTRL_SRST_REQ_BCBIST0_LEN    1
#define IO_SUBCTRL_SRST_REQ_BCBIST0_OFFSET 0

#define IO_SUBCTRL_SRST_DREQ_BCBIST0_LEN    1
#define IO_SUBCTRL_SRST_DREQ_BCBIST0_OFFSET 0

#define IO_SUBCTRL_DETECT_PERIOD_BCBIST0_LEN       2
#define IO_SUBCTRL_DETECT_PERIOD_BCBIST0_OFFSET    7
#define IO_SUBCTRL_CLK_DIV_CFG_BCBIST0_LEN         2
#define IO_SUBCTRL_CLK_DIV_CFG_BCBIST0_OFFSET      5
#define IO_SUBCTRL_DETECT_ENABLE_BCBIST0_LEN       1
#define IO_SUBCTRL_DETECT_ENABLE_BCBIST0_OFFSET    4
#define IO_SUBCTRL_BYPASS_ENABLE_BCBIST0_LEN       1
#define IO_SUBCTRL_BYPASS_ENABLE_BCBIST0_OFFSET    3
#define IO_SUBCTRL_DC_TSEL_BCBIST0_LEN             2
#define IO_SUBCTRL_DC_TSEL_BCBIST0_OFFSET          1
#define IO_SUBCTRL_FORCE_ERR_ENABLE_BCBIST0_LEN    1
#define IO_SUBCTRL_FORCE_ERR_ENABLE_BCBIST0_OFFSET 0

#define IO_SUBCTRL_DISPATCH_ERRRSP_LEN    1
#define IO_SUBCTRL_DISPATCH_ERRRSP_OFFSET 0

#define IO_SUBCTRL_GPIO6_SYN_EN_LEN    1
#define IO_SUBCTRL_GPIO6_SYN_EN_OFFSET 1
#define IO_SUBCTRL_GPIO4_SYN_EN_LEN    1
#define IO_SUBCTRL_GPIO4_SYN_EN_OFFSET 0

#define IO_SUBCTRL_SATA_REG_SAFE_CTRL_LEN    1
#define IO_SUBCTRL_SATA_REG_SAFE_CTRL_OFFSET 0

#define IO_SUBCTRL_TSENSOR_HIGH_LEN    16
#define IO_SUBCTRL_TSENSOR_HIGH_OFFSET 16
#define IO_SUBCTRL_TSENSOR_LOW_LEN     16
#define IO_SUBCTRL_TSENSOR_LOW_OFFSET  0

#define IO_SUBCTRL_TSENSOR_ULTRAHIGH_LEN    16
#define IO_SUBCTRL_TSENSOR_ULTRAHIGH_OFFSET 0

#define IO_SUBCTRL_TSENSOR_TIMEOUT_LEN    32
#define IO_SUBCTRL_TSENSOR_TIMEOUT_OFFSET 0

#define IO_SUBCTRL_TSENSOR_SAMPLE_SHIFT_NUM_LEN    4
#define IO_SUBCTRL_TSENSOR_SAMPLE_SHIFT_NUM_OFFSET 0

#define IO_SUBCTRL_TSENSOR_TEMP_SET_LEN        16
#define IO_SUBCTRL_TSENSOR_TEMP_SET_OFFSET     16
#define IO_SUBCTRL_TSENSOR_TEMP_CT_SEL_LEN     2
#define IO_SUBCTRL_TSENSOR_TEMP_CT_SEL_OFFSET  3
#define IO_SUBCTRL_TSENSOR_TEMP_CLK_SEL_LEN    1
#define IO_SUBCTRL_TSENSOR_TEMP_CLK_SEL_OFFSET 2
#define IO_SUBCTRL_TSENSOR_TEMP_EN_LEN         1
#define IO_SUBCTRL_TSENSOR_TEMP_EN_OFFSET      0

#define IO_SUBCTRL_TSENSOR_MODE_SEL_LEN    1
#define IO_SUBCTRL_TSENSOR_MODE_SEL_OFFSET 0

#define IO_SUBCTRL_TSENSOR_SOFT_SEL_LEN    1
#define IO_SUBCTRL_TSENSOR_SOFT_SEL_OFFSET 1
#define IO_SUBCTRL_TSENSOR_SOFT_EN_LEN     1
#define IO_SUBCTRL_TSENSOR_SOFT_EN_OFFSET  0

#define IO_SUBCTRL_TSENSOR_TEMP_DEBUG_LEN    1
#define IO_SUBCTRL_TSENSOR_TEMP_DEBUG_OFFSET 0

#define IO_SUBCTRL_TSENSOR_WAIT_CNT_LEN    10
#define IO_SUBCTRL_TSENSOR_WAIT_CNT_OFFSET 0

#define IO_SUBCTRL_CNT_LEN            10
#define IO_SUBCTRL_CNT_OFFSET         3
#define IO_SUBCTRL_CURR_ST_LEN        1
#define IO_SUBCTRL_CURR_ST_OFFSET     2
#define IO_SUBCTRL_M_LOCAL_SEL_LEN    1
#define IO_SUBCTRL_M_LOCAL_SEL_OFFSET 1
#define IO_SUBCTRL_M_LOCAL_EN_LEN     1
#define IO_SUBCTRL_M_LOCAL_EN_OFFSET  0

#define IO_SUBCTRL_TSENSOR_LOCAL_AVG_DATA_LEN    16
#define IO_SUBCTRL_TSENSOR_LOCAL_AVG_DATA_OFFSET 0

#define IO_SUBCTRL_TSENSOR_REMOTE0_AVG_DATA_LEN    16
#define IO_SUBCTRL_TSENSOR_REMOTE0_AVG_DATA_OFFSET 0

#define IO_SUBCTRL_TSENSOR_LOOP_START_LEN    1
#define IO_SUBCTRL_TSENSOR_LOOP_START_OFFSET 1
#define IO_SUBCTRL_TSENSOR_LOOP_LEN          1
#define IO_SUBCTRL_TSENSOR_LOOP_OFFSET       0

#define IO_SUBCTRL_TSENSOR_TIMEOUT_CLR_LEN    1
#define IO_SUBCTRL_TSENSOR_TIMEOUT_CLR_OFFSET 0

#define IO_SUBCTRL_FUNC_MBIST_CLK_SEL_LEN    1
#define IO_SUBCTRL_FUNC_MBIST_CLK_SEL_OFFSET 0

#define IO_SUBCTRL_PCIE_DAW0_ADDR_LEN    28
#define IO_SUBCTRL_PCIE_DAW0_ADDR_OFFSET 0

#define IO_SUBCTRL_PCIE_DAW0_SIZE_LEN    5
#define IO_SUBCTRL_PCIE_DAW0_SIZE_OFFSET 16
#define IO_SUBCTRL_PCIE_DAW0_DID_LEN     5
#define IO_SUBCTRL_PCIE_DAW0_DID_OFFSET  0

#define IO_SUBCTRL_PCIE_DAW1_ADDR_LEN    28
#define IO_SUBCTRL_PCIE_DAW1_ADDR_OFFSET 0

#define IO_SUBCTRL_PCIE_DAW1_SIZE_LEN    5
#define IO_SUBCTRL_PCIE_DAW1_SIZE_OFFSET 16
#define IO_SUBCTRL_PCIE_DAW1_DID_LEN     5
#define IO_SUBCTRL_PCIE_DAW1_DID_OFFSET  0

#define IO_SUBCTRL_PCIE_DAW2_ADDR_LEN    28
#define IO_SUBCTRL_PCIE_DAW2_ADDR_OFFSET 0

#define IO_SUBCTRL_PCIE_DAW2_SIZE_LEN    5
#define IO_SUBCTRL_PCIE_DAW2_SIZE_OFFSET 16
#define IO_SUBCTRL_PCIE_DAW2_DID_LEN     5
#define IO_SUBCTRL_PCIE_DAW2_DID_OFFSET  0

#define IO_SUBCTRL_PCIE_DAW3_ADDR_LEN    28
#define IO_SUBCTRL_PCIE_DAW3_ADDR_OFFSET 0

#define IO_SUBCTRL_PCIE_DAW3_SIZE_LEN    5
#define IO_SUBCTRL_PCIE_DAW3_SIZE_OFFSET 16
#define IO_SUBCTRL_PCIE_DAW3_DID_LEN     5
#define IO_SUBCTRL_PCIE_DAW3_DID_OFFSET  0

#define IO_SUBCTRL_PCIE_DAW4_ADDR_LEN    28
#define IO_SUBCTRL_PCIE_DAW4_ADDR_OFFSET 0

#define IO_SUBCTRL_PCIE_DAW4_SIZE_LEN    5
#define IO_SUBCTRL_PCIE_DAW4_SIZE_OFFSET 16
#define IO_SUBCTRL_PCIE_DAW4_DID_LEN     5
#define IO_SUBCTRL_PCIE_DAW4_DID_OFFSET  0

#define IO_SUBCTRL_PCIE_DAW5_ADDR_LEN    28
#define IO_SUBCTRL_PCIE_DAW5_ADDR_OFFSET 0

#define IO_SUBCTRL_PCIE_DAW5_SIZE_LEN    5
#define IO_SUBCTRL_PCIE_DAW5_SIZE_OFFSET 16
#define IO_SUBCTRL_PCIE_DAW5_DID_LEN     5
#define IO_SUBCTRL_PCIE_DAW5_DID_OFFSET  0

#define IO_SUBCTRL_PCIE_DAW6_ADDR_LEN    28
#define IO_SUBCTRL_PCIE_DAW6_ADDR_OFFSET 0

#define IO_SUBCTRL_PCIE_DAW6_SIZE_LEN    5
#define IO_SUBCTRL_PCIE_DAW6_SIZE_OFFSET 16
#define IO_SUBCTRL_PCIE_DAW6_DID_LEN     5
#define IO_SUBCTRL_PCIE_DAW6_DID_OFFSET  0

#define IO_SUBCTRL_PCIE_DAW7_ADDR_LEN    28
#define IO_SUBCTRL_PCIE_DAW7_ADDR_OFFSET 0

#define IO_SUBCTRL_PCIE_DAW7_SIZE_LEN    5
#define IO_SUBCTRL_PCIE_DAW7_SIZE_OFFSET 16
#define IO_SUBCTRL_PCIE_DAW7_DID_LEN     5
#define IO_SUBCTRL_PCIE_DAW7_DID_OFFSET  0

#define IO_SUBCTRL_PCIE_DAW_EN_LEN    8
#define IO_SUBCTRL_PCIE_DAW_EN_OFFSET 0

#define IO_SUBCTRL_INT_DAW_DECODER_ERR_MASK_LEN    1
#define IO_SUBCTRL_INT_DAW_DECODER_ERR_MASK_OFFSET 0

#define IO_SUBCTRL_PCIE_DECODER_ERR_LEN    4
#define IO_SUBCTRL_PCIE_DECODER_ERR_OFFSET 0

#define IO_SUBCTRL_SEL_CLK_CORE_PCIE3_LEN    2
#define IO_SUBCTRL_SEL_CLK_CORE_PCIE3_OFFSET 6
#define IO_SUBCTRL_SEL_CLK_CORE_PCIE2_LEN    2
#define IO_SUBCTRL_SEL_CLK_CORE_PCIE2_OFFSET 4
#define IO_SUBCTRL_SEL_CLK_CORE_PCIE1_LEN    2
#define IO_SUBCTRL_SEL_CLK_CORE_PCIE1_OFFSET 2
#define IO_SUBCTRL_SEL_CLK_CORE_PCIE0_LEN    2
#define IO_SUBCTRL_SEL_CLK_CORE_PCIE0_OFFSET 0

#define IO_SUBCTRL_HPM_EN_LEN    1
#define IO_SUBCTRL_HPM_EN_OFFSET 0

#define IO_SUBCTRL_HPM_DIV_LEN    6
#define IO_SUBCTRL_HPM_DIV_OFFSET 0

#define IO_SUBCTRL_HPM_PC_0_ORG_LEN    10
#define IO_SUBCTRL_HPM_PC_0_ORG_OFFSET 0

#define IO_SUBCTRL_HPM_PC_1_ORG_LEN    10
#define IO_SUBCTRL_HPM_PC_1_ORG_OFFSET 0

#define IO_SUBCTRL_HPM_PC_VALID_LEN    1
#define IO_SUBCTRL_HPM_PC_VALID_OFFSET 0

#define IO_SUBCTRL_TP_RAM_TMOD_LEN    32
#define IO_SUBCTRL_TP_RAM_TMOD_OFFSET 0

#define IO_SUBCTRL_SP_RAM_TMOD_LEN    32
#define IO_SUBCTRL_SP_RAM_TMOD_OFFSET 0

#define IO_SUBCTRL_MEM_POWER_MODE_LEN    4
#define IO_SUBCTRL_MEM_POWER_MODE_OFFSET 0

#define IO_SUBCTRL_SUBSYS_FORCE_BUSY_LEN    1
#define IO_SUBCTRL_SUBSYS_FORCE_BUSY_OFFSET 31
#define IO_SUBCTRL_MODULE_FORCE_BUSY_LEN    16
#define IO_SUBCTRL_MODULE_FORCE_BUSY_OFFSET 0

#define IO_SUBCTRL_MODULE_FORCE_IDLE_LEN    16
#define IO_SUBCTRL_MODULE_FORCE_IDLE_OFFSET 0

#define IO_SUBCTRL_AUTOLF_IDLE_CLK_CYCLE_TH_LEN    16
#define IO_SUBCTRL_AUTOLF_IDLE_CLK_CYCLE_TH_OFFSET 0

#define IO_SUBCTRL_AUTOLF_IDLE_CNT_CLR_LEN        1
#define IO_SUBCTRL_AUTOLF_IDLE_CNT_CLR_OFFSET     1
#define IO_SUBCTRL_AUTOLF_FORCE_CFG_ENABLE_LEN    1
#define IO_SUBCTRL_AUTOLF_FORCE_CFG_ENABLE_OFFSET 0

#define IO_SUBCTRL_IDLE_SUBSYS_STATUS_LEN    1
#define IO_SUBCTRL_IDLE_SUBSYS_STATUS_OFFSET 31
#define IO_SUBCTRL_IDLE_STATUS_LEN           16
#define IO_SUBCTRL_IDLE_STATUS_OFFSET        0

#define IO_SUBCTRL_IDLE_CNT_LEN    32
#define IO_SUBCTRL_IDLE_CNT_OFFSET 0

#define IO_SUBCTRL_USBC_AHBS_BIGENDIAN_USB3_LEN    1
#define IO_SUBCTRL_USBC_AHBS_BIGENDIAN_USB3_OFFSET 3
#define IO_SUBCTRL_USBC_AHBS_BIGENDIAN_USB2_LEN    1
#define IO_SUBCTRL_USBC_AHBS_BIGENDIAN_USB2_OFFSET 2
#define IO_SUBCTRL_USBC_AHBS_BIGENDIAN_USB1_LEN    1
#define IO_SUBCTRL_USBC_AHBS_BIGENDIAN_USB1_OFFSET 1
#define IO_SUBCTRL_USBC_AHBS_BIGENDIAN_USB0_LEN    1
#define IO_SUBCTRL_USBC_AHBS_BIGENDIAN_USB0_OFFSET 0

#define IO_SUBCTRL_USBC_AXI_NS_USB3_LEN    1
#define IO_SUBCTRL_USBC_AXI_NS_USB3_OFFSET 3
#define IO_SUBCTRL_USBC_AXI_NS_USB2_LEN    1
#define IO_SUBCTRL_USBC_AXI_NS_USB2_OFFSET 2
#define IO_SUBCTRL_USBC_AXI_NS_USB1_LEN    1
#define IO_SUBCTRL_USBC_AXI_NS_USB1_OFFSET 1
#define IO_SUBCTRL_USBC_AXI_NS_USB0_LEN    1
#define IO_SUBCTRL_USBC_AXI_NS_USB0_OFFSET 0

#define IO_SUBCTRL_USBC_AXIM_BIGENDIAN_USB3_LEN    1
#define IO_SUBCTRL_USBC_AXIM_BIGENDIAN_USB3_OFFSET 3
#define IO_SUBCTRL_USBC_AXIM_BIGENDIAN_USB2_LEN    1
#define IO_SUBCTRL_USBC_AXIM_BIGENDIAN_USB2_OFFSET 2
#define IO_SUBCTRL_USBC_AXIM_BIGENDIAN_USB1_LEN    1
#define IO_SUBCTRL_USBC_AXIM_BIGENDIAN_USB1_OFFSET 1
#define IO_SUBCTRL_USBC_AXIM_BIGENDIAN_USB0_LEN    1
#define IO_SUBCTRL_USBC_AXIM_BIGENDIAN_USB0_OFFSET 0

#define IO_SUBCTRL_USBC_BME_USB3_LEN    1
#define IO_SUBCTRL_USBC_BME_USB3_OFFSET 3
#define IO_SUBCTRL_USBC_BME_USB2_LEN    1
#define IO_SUBCTRL_USBC_BME_USB2_OFFSET 2
#define IO_SUBCTRL_USBC_BME_USB1_LEN    1
#define IO_SUBCTRL_USBC_BME_USB1_OFFSET 1
#define IO_SUBCTRL_USBC_BME_USB0_LEN    1
#define IO_SUBCTRL_USBC_BME_USB0_OFFSET 0

#define IO_SUBCTRL_USBC_ERR_INJ_EN_USB3_LEN    1
#define IO_SUBCTRL_USBC_ERR_INJ_EN_USB3_OFFSET 3
#define IO_SUBCTRL_USBC_ERR_INJ_EN_USB2_LEN    1
#define IO_SUBCTRL_USBC_ERR_INJ_EN_USB2_OFFSET 2
#define IO_SUBCTRL_USBC_ERR_INJ_EN_USB1_LEN    1
#define IO_SUBCTRL_USBC_ERR_INJ_EN_USB1_OFFSET 1
#define IO_SUBCTRL_USBC_ERR_INJ_EN_USB0_LEN    1
#define IO_SUBCTRL_USBC_ERR_INJ_EN_USB0_OFFSET 0

#define IO_SUBCTRL_USBC_MSI_EN_USB3_LEN    1
#define IO_SUBCTRL_USBC_MSI_EN_USB3_OFFSET 3
#define IO_SUBCTRL_USBC_MSI_EN_USB2_LEN    1
#define IO_SUBCTRL_USBC_MSI_EN_USB2_OFFSET 2
#define IO_SUBCTRL_USBC_MSI_EN_USB1_LEN    1
#define IO_SUBCTRL_USBC_MSI_EN_USB1_OFFSET 1
#define IO_SUBCTRL_USBC_MSI_EN_USB0_LEN    1
#define IO_SUBCTRL_USBC_MSI_EN_USB0_OFFSET 0

#define IO_SUBCTRL_USBC_U2_DISABLE_USB3_LEN    1
#define IO_SUBCTRL_USBC_U2_DISABLE_USB3_OFFSET 3
#define IO_SUBCTRL_USBC_U2_DISABLE_USB2_LEN    1
#define IO_SUBCTRL_USBC_U2_DISABLE_USB2_OFFSET 2
#define IO_SUBCTRL_USBC_U2_DISABLE_USB1_LEN    1
#define IO_SUBCTRL_USBC_U2_DISABLE_USB1_OFFSET 1
#define IO_SUBCTRL_USBC_U2_DISABLE_USB0_LEN    1
#define IO_SUBCTRL_USBC_U2_DISABLE_USB0_OFFSET 0

#define IO_SUBCTRL_USBC_U3_DISABLE_USB3_LEN    1
#define IO_SUBCTRL_USBC_U3_DISABLE_USB3_OFFSET 3
#define IO_SUBCTRL_USBC_U3_DISABLE_USB2_LEN    1
#define IO_SUBCTRL_USBC_U3_DISABLE_USB2_OFFSET 2
#define IO_SUBCTRL_USBC_U3_DISABLE_USB1_LEN    1
#define IO_SUBCTRL_USBC_U3_DISABLE_USB1_OFFSET 1
#define IO_SUBCTRL_USBC_U3_DISABLE_USB0_LEN    1
#define IO_SUBCTRL_USBC_U3_DISABLE_USB0_OFFSET 0

#define IO_SUBCTRL_USBC_UTMI8BIT_EN_USB3_LEN    1
#define IO_SUBCTRL_USBC_UTMI8BIT_EN_USB3_OFFSET 3
#define IO_SUBCTRL_USBC_UTMI8BIT_EN_USB2_LEN    1
#define IO_SUBCTRL_USBC_UTMI8BIT_EN_USB2_OFFSET 2
#define IO_SUBCTRL_USBC_UTMI8BIT_EN_USB1_LEN    1
#define IO_SUBCTRL_USBC_UTMI8BIT_EN_USB1_OFFSET 1
#define IO_SUBCTRL_USBC_UTMI8BIT_EN_USB0_LEN    1
#define IO_SUBCTRL_USBC_UTMI8BIT_EN_USB0_OFFSET 0

#define IO_SUBCTRL_USBC_UTMI_ULPI_SEL_USB3_LEN    1
#define IO_SUBCTRL_USBC_UTMI_ULPI_SEL_USB3_OFFSET 3
#define IO_SUBCTRL_USBC_UTMI_ULPI_SEL_USB2_LEN    1
#define IO_SUBCTRL_USBC_UTMI_ULPI_SEL_USB2_OFFSET 2
#define IO_SUBCTRL_USBC_UTMI_ULPI_SEL_USB1_LEN    1
#define IO_SUBCTRL_USBC_UTMI_ULPI_SEL_USB1_OFFSET 1
#define IO_SUBCTRL_USBC_UTMI_ULPI_SEL_USB0_LEN    1
#define IO_SUBCTRL_USBC_UTMI_ULPI_SEL_USB0_OFFSET 0

#define IO_SUBCTRL_FSEL_USBPHY3_LEN    3
#define IO_SUBCTRL_FSEL_USBPHY3_OFFSET 8
#define IO_SUBCTRL_FSEL_USBPHY2_LEN    3
#define IO_SUBCTRL_FSEL_USBPHY2_OFFSET 4
#define IO_SUBCTRL_FSEL_USBPHY1_LEN    3
#define IO_SUBCTRL_FSEL_USBPHY1_OFFSET 0

#define IO_SUBCTRL_UTMI_DATABUS_USBPHY_LEN    3
#define IO_SUBCTRL_UTMI_DATABUS_USBPHY_OFFSET 0

#define IO_SUBCTRL_BIST_OVRD_EN_USBPHY_LEN           3
#define IO_SUBCTRL_BIST_OVRD_EN_USBPHY_OFFSET        6
#define IO_SUBCTRL_PHY_BC12_OVRD_EN_USBPHY_LEN       3
#define IO_SUBCTRL_PHY_BC12_OVRD_EN_USBPHY_OFFSET    3
#define IO_SUBCTRL_PHY_CFG_ANA_OVRD_EN_USBPHY_LEN    3
#define IO_SUBCTRL_PHY_CFG_ANA_OVRD_EN_USBPHY_OFFSET 0

#define IO_SUBCTRL_TEST_IDDQ_USBPHY_LEN       3
#define IO_SUBCTRL_TEST_IDDQ_USBPHY_OFFSET    18
#define IO_SUBCTRL_HSXCVREXTCTL_USBPHY_LEN    3
#define IO_SUBCTRL_HSXCVREXTCTL_USBPHY_OFFSET 15
#define IO_SUBCTRL_COMMONONN_USBPHY_LEN       3
#define IO_SUBCTRL_COMMONONN_USBPHY_OFFSET    12
#define IO_SUBCTRL_BYPASSSEL_USBPHY_LEN       3
#define IO_SUBCTRL_BYPASSSEL_USBPHY_OFFSET    9
#define IO_SUBCTRL_BYPASSEN_USBPHY_LEN        3
#define IO_SUBCTRL_BYPASSEN_USBPHY_OFFSET     6
#define IO_SUBCTRL_BYPASSDMDATA_USBPHY_LEN    3
#define IO_SUBCTRL_BYPASSDMDATA_USBPHY_OFFSET 3
#define IO_SUBCTRL_BYPASSDPDATA_USBPHY_LEN    3
#define IO_SUBCTRL_BYPASSDPDATA_USBPHY_OFFSET 0

#define IO_SUBCTRL_PHY_ANA_COMMON_RESV_USBPHY2_LEN    16
#define IO_SUBCTRL_PHY_ANA_COMMON_RESV_USBPHY2_OFFSET 16
#define IO_SUBCTRL_PHY_ANA_COMMON_RESV_USBPHY1_LEN    16
#define IO_SUBCTRL_PHY_ANA_COMMON_RESV_USBPHY1_OFFSET 0

#define IO_SUBCTRL_PHY_ANA_COMMON_RESV_USBPHY3_LEN    16
#define IO_SUBCTRL_PHY_ANA_COMMON_RESV_USBPHY3_OFFSET 0

#define IO_SUBCTRL_PHY_ANA_PORT_RESV_USBPHY2_LEN    16
#define IO_SUBCTRL_PHY_ANA_PORT_RESV_USBPHY2_OFFSET 16
#define IO_SUBCTRL_PHY_ANA_PORT_RESV_USBPHY1_LEN    16
#define IO_SUBCTRL_PHY_ANA_PORT_RESV_USBPHY1_OFFSET 0

#define IO_SUBCTRL_PHY_ANA_PORT_RESV_USBPHY3_LEN    16
#define IO_SUBCTRL_PHY_ANA_PORT_RESV_USBPHY3_OFFSET 0

#define IO_SUBCTRL_PHY_CKTST_SEL_USBPHY_LEN      3
#define IO_SUBCTRL_PHY_CKTST_SEL_USBPHY_OFFSET   27
#define IO_SUBCTRL_PHY_BG_TST_USBPHY3_LEN        2
#define IO_SUBCTRL_PHY_BG_TST_USBPHY3_OFFSET     25
#define IO_SUBCTRL_PHY_BG_TST_USBPHY2_LEN        2
#define IO_SUBCTRL_PHY_BG_TST_USBPHY2_OFFSET     23
#define IO_SUBCTRL_PHY_BG_TST_USBPHY1_LEN        2
#define IO_SUBCTRL_PHY_BG_TST_USBPHY1_OFFSET     21
#define IO_SUBCTRL_PHY_BG_MT_TUNE_USBPHY3_LEN    3
#define IO_SUBCTRL_PHY_BG_MT_TUNE_USBPHY3_OFFSET 18
#define IO_SUBCTRL_PHY_BG_MT_TUNE_USBPHY2_LEN    3
#define IO_SUBCTRL_PHY_BG_MT_TUNE_USBPHY2_OFFSET 15
#define IO_SUBCTRL_PHY_BG_MT_TUNE_USBPHY1_LEN    3
#define IO_SUBCTRL_PHY_BG_MT_TUNE_USBPHY1_OFFSET 12
#define IO_SUBCTRL_PHY_BG_MT_EN_USBPHY_LEN       3
#define IO_SUBCTRL_PHY_BG_MT_EN_USBPHY_OFFSET    9
#define IO_SUBCTRL_PHY_BG_DETEC_EN_USBPHY_LEN    3
#define IO_SUBCTRL_PHY_BG_DETEC_EN_USBPHY_OFFSET 6
#define IO_SUBCTRL_PHY_ATP_SEL_USBPHY3_LEN       2
#define IO_SUBCTRL_PHY_ATP_SEL_USBPHY3_OFFSET    4
#define IO_SUBCTRL_PHY_ATP_SEL_USBPHY2_LEN       2
#define IO_SUBCTRL_PHY_ATP_SEL_USBPHY2_OFFSET    2
#define IO_SUBCTRL_PHY_ATP_SEL_USBPHY1_LEN       2
#define IO_SUBCTRL_PHY_ATP_SEL_USBPHY1_OFFSET    0

#define IO_SUBCTRL_PHY_BIST_REPEAT_USBPHY_LEN           3
#define IO_SUBCTRL_PHY_BIST_REPEAT_USBPHY_OFFSET        27
#define IO_SUBCTRL_PHY_BIST_MODE_USBPHY_LEN             3
#define IO_SUBCTRL_PHY_BIST_MODE_USBPHY_OFFSET          24
#define IO_SUBCTRL_PHY_BIST_LOOPBACKENB_USBPHY_LEN      3
#define IO_SUBCTRL_PHY_BIST_LOOPBACKENB_USBPHY_OFFSET   21
#define IO_SUBCTRL_PHY_BIST_EN_USBPHY_LEN               3
#define IO_SUBCTRL_PHY_BIST_EN_USBPHY_OFFSET            18
#define IO_SUBCTRL_PHY_BIST_DATABUS_USBPHY_LEN          3
#define IO_SUBCTRL_PHY_BIST_DATABUS_USBPHY_OFFSET       15
#define IO_SUBCTRL_PHY_BIST_CONTROLLER_EN_USBPHY_LEN    3
#define IO_SUBCTRL_PHY_BIST_CONTROLLER_EN_USBPHY_OFFSET 12
#define IO_SUBCTRL_PHY_BG_TX_VREF_TUNE_USBPHY3_LEN      4
#define IO_SUBCTRL_PHY_BG_TX_VREF_TUNE_USBPHY3_OFFSET   8
#define IO_SUBCTRL_PHY_BG_TX_VREF_TUNE_USBPHY2_LEN      4
#define IO_SUBCTRL_PHY_BG_TX_VREF_TUNE_USBPHY2_OFFSET   4
#define IO_SUBCTRL_PHY_BG_TX_VREF_TUNE_USBPHY1_LEN      4
#define IO_SUBCTRL_PHY_BG_TX_VREF_TUNE_USBPHY1_OFFSET   0

#define IO_SUBCTRL_PHY_LDO_VREF_TUNE_USBPHY3_LEN     3
#define IO_SUBCTRL_PHY_LDO_VREF_TUNE_USBPHY3_OFFSET  18
#define IO_SUBCTRL_PHY_LDO_VREF_TUNE_USBPHY2_LEN     3
#define IO_SUBCTRL_PHY_LDO_VREF_TUNE_USBPHY2_OFFSET  15
#define IO_SUBCTRL_PHY_LDO_VREF_TUNE_USBPHY1_LEN     3
#define IO_SUBCTRL_PHY_LDO_VREF_TUNE_USBPHY1_OFFSET  12
#define IO_SUBCTRL_PHY_LDO_TST_EN_USBPHY_LEN         3
#define IO_SUBCTRL_PHY_LDO_TST_EN_USBPHY_OFFSET      9
#define IO_SUBCTRL_PHY_BIST_TESTBURNIN_USBPHY_LEN    3
#define IO_SUBCTRL_PHY_BIST_TESTBURNIN_USBPHY_OFFSET 6
#define IO_SUBCTRL_PHY_BIST_SPEED_USBPHY3_LEN        2
#define IO_SUBCTRL_PHY_BIST_SPEED_USBPHY3_OFFSET     4
#define IO_SUBCTRL_PHY_BIST_SPEED_USBPHY2_LEN        2
#define IO_SUBCTRL_PHY_BIST_SPEED_USBPHY2_OFFSET     2
#define IO_SUBCTRL_PHY_BIST_SPEED_USBPHY1_LEN        2
#define IO_SUBCTRL_PHY_BIST_SPEED_USBPHY1_OFFSET     0

#define IO_SUBCTRL_PHY_RT_CODE_FB_SEL_USBPHY_LEN      3
#define IO_SUBCTRL_PHY_RT_CODE_FB_SEL_USBPHY_OFFSET   27
#define IO_SUBCTRL_PHY_PLL_TEST_SEL_USBPHY3_LEN       3
#define IO_SUBCTRL_PHY_PLL_TEST_SEL_USBPHY3_OFFSET    24
#define IO_SUBCTRL_PHY_PLL_TEST_SEL_USBPHY2_LEN       3
#define IO_SUBCTRL_PHY_PLL_TEST_SEL_USBPHY2_OFFSET    21
#define IO_SUBCTRL_PHY_PLL_TEST_SEL_USBPHY1_LEN       3
#define IO_SUBCTRL_PHY_PLL_TEST_SEL_USBPHY1_OFFSET    18
#define IO_SUBCTRL_PHY_PLL_TEST_EN_USBPHY_LEN         3
#define IO_SUBCTRL_PHY_PLL_TEST_EN_USBPHY_OFFSET      15
#define IO_SUBCTRL_PHY_PLL_FORCE_LOCK_USBPHY_LEN      3
#define IO_SUBCTRL_PHY_PLL_FORCE_LOCK_USBPHY_OFFSET   12
#define IO_SUBCTRL_PHY_PLL_FB_DIV_SEL_USBPHY_LEN      3
#define IO_SUBCTRL_PHY_PLL_FB_DIV_SEL_USBPHY_OFFSET   9
#define IO_SUBCTRL_PHY_PLL_FASTLOCK_SEL_USBPHY_LEN    3
#define IO_SUBCTRL_PHY_PLL_FASTLOCK_SEL_USBPHY_OFFSET 6
#define IO_SUBCTRL_PHY_PLL_FASTLOCK_PD_USBPHY_LEN     3
#define IO_SUBCTRL_PHY_PLL_FASTLOCK_PD_USBPHY_OFFSET  3
#define IO_SUBCTRL_PHY_PLL_EN_LCKDET_USBPHY_LEN       3
#define IO_SUBCTRL_PHY_PLL_EN_LCKDET_USBPHY_OFFSET    0

#define IO_SUBCTRL_PHY_RX_HS_EN_USBPHY_LEN            3
#define IO_SUBCTRL_PHY_RX_HS_EN_USBPHY_OFFSET         29
#define IO_SUBCTRL_PHY_RX_HS_CLK180_EN_USBPHY_LEN     3
#define IO_SUBCTRL_PHY_RX_HS_CLK180_EN_USBPHY_OFFSET  26
#define IO_SUBCTRL_PHY_RX_HS_BUF_SEL_USBPHY3_LEN      2
#define IO_SUBCTRL_PHY_RX_HS_BUF_SEL_USBPHY3_OFFSET   24
#define IO_SUBCTRL_PHY_RX_HS_BUF_SEL_USBPHY2_LEN      2
#define IO_SUBCTRL_PHY_RX_HS_BUF_SEL_USBPHY2_OFFSET   22
#define IO_SUBCTRL_PHY_RX_HS_BUF_SEL_USBPHY1_LEN      2
#define IO_SUBCTRL_PHY_RX_HS_BUF_SEL_USBPHY1_OFFSET   20
#define IO_SUBCTRL_PHY_RX_DISC_IL_SEL_USBPHY3_LEN     4
#define IO_SUBCTRL_PHY_RX_DISC_IL_SEL_USBPHY3_OFFSET  16
#define IO_SUBCTRL_PHY_RX_DISC_IL_SEL_USBPHY2_LEN     4
#define IO_SUBCTRL_PHY_RX_DISC_IL_SEL_USBPHY2_OFFSET  12
#define IO_SUBCTRL_PHY_RX_DISC_IL_SEL_USBPHY1_LEN     4
#define IO_SUBCTRL_PHY_RX_DISC_IL_SEL_USBPHY1_OFFSET  8
#define IO_SUBCTRL_PHY_RX_DCD_VREF_SEL_USBPHY3_LEN    2
#define IO_SUBCTRL_PHY_RX_DCD_VREF_SEL_USBPHY3_OFFSET 4
#define IO_SUBCTRL_PHY_RX_DCD_VREF_SEL_USBPHY2_LEN    2
#define IO_SUBCTRL_PHY_RX_DCD_VREF_SEL_USBPHY2_OFFSET 2
#define IO_SUBCTRL_PHY_RX_DCD_VREF_SEL_USBPHY1_LEN    2
#define IO_SUBCTRL_PHY_RX_DCD_VREF_SEL_USBPHY1_OFFSET 0

#define IO_SUBCTRL_PHY_RX_SRC_VREF_SEL_USBPHY3_LEN          2
#define IO_SUBCTRL_PHY_RX_SRC_VREF_SEL_USBPHY3_OFFSET       28
#define IO_SUBCTRL_PHY_RX_SRC_VREF_SEL_USBPHY2_LEN          2
#define IO_SUBCTRL_PHY_RX_SRC_VREF_SEL_USBPHY2_OFFSET       26
#define IO_SUBCTRL_PHY_RX_SRC_VREF_SEL_USBPHY1_LEN          2
#define IO_SUBCTRL_PHY_RX_SRC_VREF_SEL_USBPHY1_OFFSET       24
#define IO_SUBCTRL_PHY_RX_SQ_FILTER_EN_USBPHY_LEN           3
#define IO_SUBCTRL_PHY_RX_SQ_FILTER_EN_USBPHY_OFFSET        21
#define IO_SUBCTRL_PHY_RX_SQ_EN_USBPHY_LEN                  3
#define IO_SUBCTRL_PHY_RX_SQ_EN_USBPHY_OFFSET               18
#define IO_SUBCTRL_PHY_RX_SQ_BIAS_SEL_USBPHY3_LEN           2
#define IO_SUBCTRL_PHY_RX_SQ_BIAS_SEL_USBPHY3_OFFSET        16
#define IO_SUBCTRL_PHY_RX_SQ_BIAS_SEL_USBPHY2_LEN           2
#define IO_SUBCTRL_PHY_RX_SQ_BIAS_SEL_USBPHY2_OFFSET        14
#define IO_SUBCTRL_PHY_RX_SQ_BIAS_SEL_USBPHY1_LEN           2
#define IO_SUBCTRL_PHY_RX_SQ_BIAS_SEL_USBPHY1_OFFSET        12
#define IO_SUBCTRL_PHY_RX_SELFBIAS_EN_USBPHY_LEN            3
#define IO_SUBCTRL_PHY_RX_SELFBIAS_EN_USBPHY_OFFSET         9
#define IO_SUBCTRL_PHY_RX_HS_VALID_DELAY_SEL_USBPHY3_LEN    2
#define IO_SUBCTRL_PHY_RX_HS_VALID_DELAY_SEL_USBPHY3_OFFSET 7
#define IO_SUBCTRL_PHY_RX_HS_VALID_DELAY_SEL_USBPHY2_LEN    2
#define IO_SUBCTRL_PHY_RX_HS_VALID_DELAY_SEL_USBPHY2_OFFSET 5
#define IO_SUBCTRL_PHY_RX_HS_VALID_DELAY_SEL_USBPHY1_LEN    2
#define IO_SUBCTRL_PHY_RX_HS_VALID_DELAY_SEL_USBPHY1_OFFSET 3
#define IO_SUBCTRL_PHY_RX_HS_PATH_EN_USBPHY_LEN             3
#define IO_SUBCTRL_PHY_RX_HS_PATH_EN_USBPHY_OFFSET          0

#define IO_SUBCTRL_PHY_RX_TST_SEL_USBPHY3_LEN         3
#define IO_SUBCTRL_PHY_RX_TST_SEL_USBPHY3_OFFSET      27
#define IO_SUBCTRL_PHY_RX_TST_SEL_USBPHY2_LEN         3
#define IO_SUBCTRL_PHY_RX_TST_SEL_USBPHY2_OFFSET      24
#define IO_SUBCTRL_PHY_RX_TST_SEL_USBPHY1_LEN         3
#define IO_SUBCTRL_PHY_RX_TST_SEL_USBPHY1_OFFSET      21
#define IO_SUBCTRL_PHY_RX_TST_EN_USBPHY_LEN           3
#define IO_SUBCTRL_PHY_RX_TST_EN_USBPHY_OFFSET        18
#define IO_SUBCTRL_PHY_RX_TEST_VREF_SEL_USBPHY_LEN    3
#define IO_SUBCTRL_PHY_RX_TEST_VREF_SEL_USBPHY_OFFSET 15
#define IO_SUBCTRL_PHY_RX_SQ_IN_SEL_USBPHY_LEN        3
#define IO_SUBCTRL_PHY_RX_SQ_IN_SEL_USBPHY_OFFSET     12
#define IO_SUBCTRL_PHY_RX_SQ_IL_SEL_USBPHY3_LEN       4
#define IO_SUBCTRL_PHY_RX_SQ_IL_SEL_USBPHY3_OFFSET    8
#define IO_SUBCTRL_PHY_RX_SQ_IL_SEL_USBPHY2_LEN       4
#define IO_SUBCTRL_PHY_RX_SQ_IL_SEL_USBPHY2_OFFSET    4
#define IO_SUBCTRL_PHY_RX_SQ_IL_SEL_USBPHY1_LEN       4
#define IO_SUBCTRL_PHY_RX_SQ_IL_SEL_USBPHY1_OFFSET    0

#define IO_SUBCTRL_PHY_TX_FLS_CLKDIVBY4_USBPHY_LEN    3
#define IO_SUBCTRL_PHY_TX_FLS_CLKDIVBY4_USBPHY_OFFSET 27
#define IO_SUBCTRL_PHY_TX_FLS_CLKDIVBY2_USBPHY_LEN    3
#define IO_SUBCTRL_PHY_TX_FLS_CLKDIVBY2_USBPHY_OFFSET 24
#define IO_SUBCTRL_PHY_TX_CODE_SEL_USBPHY3_LEN        2
#define IO_SUBCTRL_PHY_TX_CODE_SEL_USBPHY3_OFFSET     22
#define IO_SUBCTRL_PHY_TX_CODE_SEL_USBPHY2_LEN        2
#define IO_SUBCTRL_PHY_TX_CODE_SEL_USBPHY2_OFFSET     20
#define IO_SUBCTRL_PHY_TX_CODE_SEL_USBPHY1_LEN        2
#define IO_SUBCTRL_PHY_TX_CODE_SEL_USBPHY1_OFFSET     18
#define IO_SUBCTRL_PHY_TOPLDO_TRIM_USBPHY3_LEN        2
#define IO_SUBCTRL_PHY_TOPLDO_TRIM_USBPHY3_OFFSET     16
#define IO_SUBCTRL_PHY_TOPLDO_TRIM_USBPHY2_LEN        2
#define IO_SUBCTRL_PHY_TOPLDO_TRIM_USBPHY2_OFFSET     14
#define IO_SUBCTRL_PHY_TOPLDO_TRIM_USBPHY1_LEN        2
#define IO_SUBCTRL_PHY_TOPLDO_TRIM_USBPHY1_OFFSET     12
#define IO_SUBCTRL_PHY_TOPLDO_TEST_USBPHY3_LEN        2
#define IO_SUBCTRL_PHY_TOPLDO_TEST_USBPHY3_OFFSET     10
#define IO_SUBCTRL_PHY_TOPLDO_TEST_USBPHY2_LEN        2
#define IO_SUBCTRL_PHY_TOPLDO_TEST_USBPHY2_OFFSET     8
#define IO_SUBCTRL_PHY_TOPLDO_TEST_USBPHY1_LEN        2
#define IO_SUBCTRL_PHY_TOPLDO_TEST_USBPHY1_OFFSET     6
#define IO_SUBCTRL_PHY_RX_VBUS_VREF_USBPHY3_LEN       2
#define IO_SUBCTRL_PHY_RX_VBUS_VREF_USBPHY3_OFFSET    4
#define IO_SUBCTRL_PHY_RX_VBUS_VREF_USBPHY2_LEN       2
#define IO_SUBCTRL_PHY_RX_VBUS_VREF_USBPHY2_OFFSET    2
#define IO_SUBCTRL_PHY_RX_VBUS_VREF_USBPHY1_LEN       2
#define IO_SUBCTRL_PHY_RX_VBUS_VREF_USBPHY1_OFFSET    0

#define IO_SUBCTRL_PHY_TX_HS_DRVCAP_DE_SEL_USBPHY3_LEN    4
#define IO_SUBCTRL_PHY_TX_HS_DRVCAP_DE_SEL_USBPHY3_OFFSET 28
#define IO_SUBCTRL_PHY_TX_HS_DRVCAP_DE_SEL_USBPHY2_LEN    4
#define IO_SUBCTRL_PHY_TX_HS_DRVCAP_DE_SEL_USBPHY2_OFFSET 24
#define IO_SUBCTRL_PHY_TX_HS_DRVCAP_DE_SEL_USBPHY1_LEN    4
#define IO_SUBCTRL_PHY_TX_HS_DRVCAP_DE_SEL_USBPHY1_OFFSET 20
#define IO_SUBCTRL_PHY_TX_HS_DE_IBSEL_USBPHY3_LEN         4
#define IO_SUBCTRL_PHY_TX_HS_DE_IBSEL_USBPHY3_OFFSET      16
#define IO_SUBCTRL_PHY_TX_HS_DE_IBSEL_USBPHY2_LEN         4
#define IO_SUBCTRL_PHY_TX_HS_DE_IBSEL_USBPHY2_OFFSET      12
#define IO_SUBCTRL_PHY_TX_HS_DE_IBSEL_USBPHY1_LEN         4
#define IO_SUBCTRL_PHY_TX_HS_DE_IBSEL_USBPHY1_OFFSET      8
#define IO_SUBCTRL_PHY_TX_HS_DE_EN_USBPHY_LEN             3
#define IO_SUBCTRL_PHY_TX_HS_DE_EN_USBPHY_OFFSET          3
#define IO_SUBCTRL_PHY_TX_FLS_SR_SELSLOW_USBPHY_LEN       3
#define IO_SUBCTRL_PHY_TX_FLS_SR_SELSLOW_USBPHY_OFFSET    0

#define IO_SUBCTRL_PHY_VCO_ST_PD_USBPHY_LEN                  3
#define IO_SUBCTRL_PHY_VCO_ST_PD_USBPHY_OFFSET               27
#define IO_SUBCTRL_PHY_VCO_ST_MCU_EN_USBPHY_LEN              3
#define IO_SUBCTRL_PHY_VCO_ST_MCU_EN_USBPHY_OFFSET           24
#define IO_SUBCTRL_PHY_TX_HS_DRVCAP_MAIN_SEL_USBPHY3_LEN     4
#define IO_SUBCTRL_PHY_TX_HS_DRVCAP_MAIN_SEL_USBPHY3_OFFSET  20
#define IO_SUBCTRL_PHY_TX_HS_DRVCAP_MAIN_SEL_USBPHY2_LEN     4
#define IO_SUBCTRL_PHY_TX_HS_DRVCAP_MAIN_SEL_USBPHY2_OFFSET  16
#define IO_SUBCTRL_PHY_TX_HS_DRVCAP_MAIN_SEL_USBPHY1_LEN     4
#define IO_SUBCTRL_PHY_TX_HS_DRVCAP_MAIN_SEL_USBPHY1_OFFSET  12
#define IO_SUBCTRL_PHY_TX_HS_DRVCAP_MAIN_SELH_USBPHY3_LEN    2
#define IO_SUBCTRL_PHY_TX_HS_DRVCAP_MAIN_SELH_USBPHY3_OFFSET 7
#define IO_SUBCTRL_PHY_TX_HS_DRVCAP_MAIN_SELH_USBPHY2_LEN    2
#define IO_SUBCTRL_PHY_TX_HS_DRVCAP_MAIN_SELH_USBPHY2_OFFSET 5
#define IO_SUBCTRL_PHY_TX_HS_DRVCAP_MAIN_SELH_USBPHY1_LEN    2
#define IO_SUBCTRL_PHY_TX_HS_DRVCAP_MAIN_SELH_USBPHY1_OFFSET 3
#define IO_SUBCTRL_PHY_TX_HS_DRVCAP_DE_SELH_USBPHY_LEN       3
#define IO_SUBCTRL_PHY_TX_HS_DRVCAP_DE_SELH_USBPHY_OFFSET    0

#define IO_SUBCTRL_PHY_TX_HS_MAIN_IBSEL_USBPHY3_LEN    6
#define IO_SUBCTRL_PHY_TX_HS_MAIN_IBSEL_USBPHY3_OFFSET 16
#define IO_SUBCTRL_PHY_TX_HS_MAIN_IBSEL_USBPHY2_LEN    6
#define IO_SUBCTRL_PHY_TX_HS_MAIN_IBSEL_USBPHY2_OFFSET 8
#define IO_SUBCTRL_PHY_TX_HS_MAIN_IBSEL_USBPHY1_LEN    6
#define IO_SUBCTRL_PHY_TX_HS_MAIN_IBSEL_USBPHY1_OFFSET 0

#define IO_SUBCTRL_PHY_TX_TEST_USBPHY3_LEN    8
#define IO_SUBCTRL_PHY_TX_TEST_USBPHY3_OFFSET 16
#define IO_SUBCTRL_PHY_TX_TEST_USBPHY2_LEN    8
#define IO_SUBCTRL_PHY_TX_TEST_USBPHY2_OFFSET 8
#define IO_SUBCTRL_PHY_TX_TEST_USBPHY1_LEN    8
#define IO_SUBCTRL_PHY_TX_TEST_USBPHY1_OFFSET 0

#define IO_SUBCTRL_PHY_PLL_CP_USBPHY3_LEN         4
#define IO_SUBCTRL_PHY_PLL_CP_USBPHY3_OFFSET      26
#define IO_SUBCTRL_PHY_PLL_CP_USBPHY2_LEN         4
#define IO_SUBCTRL_PHY_PLL_CP_USBPHY2_OFFSET      22
#define IO_SUBCTRL_PHY_PLL_CP_USBPHY1_LEN         4
#define IO_SUBCTRL_PHY_PLL_CP_USBPHY1_OFFSET      18
#define IO_SUBCTRL_VBUSVLDEXT_USBPHY_LEN          3
#define IO_SUBCTRL_VBUSVLDEXT_USBPHY_OFFSET       15
#define IO_SUBCTRL_PHY_BG_SOFT_EN_USBPHY_LEN      3
#define IO_SUBCTRL_PHY_BG_SOFT_EN_USBPHY_OFFSET   12
#define IO_SUBCTRL_PHY_VPBIAS_VSEL_USBPHY3_LEN    2
#define IO_SUBCTRL_PHY_VPBIAS_VSEL_USBPHY3_OFFSET 10
#define IO_SUBCTRL_PHY_VPBIAS_VSEL_USBPHY2_LEN    2
#define IO_SUBCTRL_PHY_VPBIAS_VSEL_USBPHY2_OFFSET 8
#define IO_SUBCTRL_PHY_VPBIAS_VSEL_USBPHY1_LEN    2
#define IO_SUBCTRL_PHY_VPBIAS_VSEL_USBPHY1_OFFSET 6
#define IO_SUBCTRL_PHY_VPBIAS_ISEL_USBPHY3_LEN    2
#define IO_SUBCTRL_PHY_VPBIAS_ISEL_USBPHY3_OFFSET 4
#define IO_SUBCTRL_PHY_VPBIAS_ISEL_USBPHY2_LEN    2
#define IO_SUBCTRL_PHY_VPBIAS_ISEL_USBPHY2_OFFSET 2
#define IO_SUBCTRL_PHY_VPBIAS_ISEL_USBPHY1_LEN    2
#define IO_SUBCTRL_PHY_VPBIAS_ISEL_USBPHY1_OFFSET 0

#define IO_SUBCTRL_USB0_ARUSER_31_0_LEN    32
#define IO_SUBCTRL_USB0_ARUSER_31_0_OFFSET 0

#define IO_SUBCTRL_USB0_ARUSER_63_49_LEN    15
#define IO_SUBCTRL_USB0_ARUSER_63_49_OFFSET 17
#define IO_SUBCTRL_USB0_ARUSER_48_46_LEN    3
#define IO_SUBCTRL_USB0_ARUSER_48_46_OFFSET 14
#define IO_SUBCTRL_USB0_ARUSER_45_39_LEN    7
#define IO_SUBCTRL_USB0_ARUSER_45_39_OFFSET 7
#define IO_SUBCTRL_USB0_ARUSER_NS_LEN       1
#define IO_SUBCTRL_USB0_ARUSER_NS_OFFSET    6
#define IO_SUBCTRL_USB0_ARUSER_37_32_LEN    6
#define IO_SUBCTRL_USB0_ARUSER_37_32_OFFSET 0

#define IO_SUBCTRL_USB0_ARUSER_95_64_LEN    32
#define IO_SUBCTRL_USB0_ARUSER_95_64_OFFSET 0

#define IO_SUBCTRL_USB0_ARUSER_103_96_LEN    8
#define IO_SUBCTRL_USB0_ARUSER_103_96_OFFSET 0

#define IO_SUBCTRL_USB0_AWUSER_31_0_LEN    32
#define IO_SUBCTRL_USB0_AWUSER_31_0_OFFSET 0

#define IO_SUBCTRL_USB0_AWUSER_63_49_LEN    15
#define IO_SUBCTRL_USB0_AWUSER_63_49_OFFSET 17
#define IO_SUBCTRL_USB0_AWUSER_48_46_LEN    3
#define IO_SUBCTRL_USB0_AWUSER_48_46_OFFSET 14
#define IO_SUBCTRL_USB0_AWUSER_45_39_LEN    7
#define IO_SUBCTRL_USB0_AWUSER_45_39_OFFSET 7
#define IO_SUBCTRL_USB0_AWUSER_NS_LEN       1
#define IO_SUBCTRL_USB0_AWUSER_NS_OFFSET    6
#define IO_SUBCTRL_USB0_AWUSER_37_32_LEN    6
#define IO_SUBCTRL_USB0_AWUSER_37_32_OFFSET 0

#define IO_SUBCTRL_USB0_AWUSER_95_64_LEN    32
#define IO_SUBCTRL_USB0_AWUSER_95_64_OFFSET 0

#define IO_SUBCTRL_USB0_AWUSER_103_96_LEN    8
#define IO_SUBCTRL_USB0_AWUSER_103_96_OFFSET 0

#define IO_SUBCTRL_USB1_ARUSER_31_0_LEN    32
#define IO_SUBCTRL_USB1_ARUSER_31_0_OFFSET 0

#define IO_SUBCTRL_USB1_ARUSER_63_49_LEN    15
#define IO_SUBCTRL_USB1_ARUSER_63_49_OFFSET 17
#define IO_SUBCTRL_USB1_ARUSER_48_46_LEN    3
#define IO_SUBCTRL_USB1_ARUSER_48_46_OFFSET 14
#define IO_SUBCTRL_USB1_ARUSER_45_39_LEN    7
#define IO_SUBCTRL_USB1_ARUSER_45_39_OFFSET 7
#define IO_SUBCTRL_USB1_ARUSER_NS_LEN       1
#define IO_SUBCTRL_USB1_ARUSER_NS_OFFSET    6
#define IO_SUBCTRL_USB1_ARUSER_37_32_LEN    6
#define IO_SUBCTRL_USB1_ARUSER_37_32_OFFSET 0

#define IO_SUBCTRL_USB1_ARUSER_95_64_LEN    32
#define IO_SUBCTRL_USB1_ARUSER_95_64_OFFSET 0

#define IO_SUBCTRL_USB1_ARUSER_103_96_LEN    8
#define IO_SUBCTRL_USB1_ARUSER_103_96_OFFSET 0

#define IO_SUBCTRL_USB1_AWUSER_31_0_LEN    32
#define IO_SUBCTRL_USB1_AWUSER_31_0_OFFSET 0

#define IO_SUBCTRL_USB1_AWUSER_63_49_LEN    15
#define IO_SUBCTRL_USB1_AWUSER_63_49_OFFSET 17
#define IO_SUBCTRL_USB1_AWUSER_48_46_LEN    3
#define IO_SUBCTRL_USB1_AWUSER_48_46_OFFSET 14
#define IO_SUBCTRL_USB1_AWUSER_45_39_LEN    7
#define IO_SUBCTRL_USB1_AWUSER_45_39_OFFSET 7
#define IO_SUBCTRL_USB1_AWUSER_NS_LEN       1
#define IO_SUBCTRL_USB1_AWUSER_NS_OFFSET    6
#define IO_SUBCTRL_USB1_AWUSER_37_32_LEN    6
#define IO_SUBCTRL_USB1_AWUSER_37_32_OFFSET 0

#define IO_SUBCTRL_USB1_AWUSER_95_64_LEN    32
#define IO_SUBCTRL_USB1_AWUSER_95_64_OFFSET 0

#define IO_SUBCTRL_USB1_AWUSER_103_96_LEN    8
#define IO_SUBCTRL_USB1_AWUSER_103_96_OFFSET 0

#define IO_SUBCTRL_USB2_ARUSER_31_0_LEN    32
#define IO_SUBCTRL_USB2_ARUSER_31_0_OFFSET 0

#define IO_SUBCTRL_USB2_ARUSER_63_49_LEN    15
#define IO_SUBCTRL_USB2_ARUSER_63_49_OFFSET 17
#define IO_SUBCTRL_USB2_ARUSER_48_46_LEN    3
#define IO_SUBCTRL_USB2_ARUSER_48_46_OFFSET 14
#define IO_SUBCTRL_USB2_ARUSER_45_39_LEN    7
#define IO_SUBCTRL_USB2_ARUSER_45_39_OFFSET 7
#define IO_SUBCTRL_USB2_ARUSER_NS_LEN       1
#define IO_SUBCTRL_USB2_ARUSER_NS_OFFSET    6
#define IO_SUBCTRL_USB2_ARUSER_37_32_LEN    6
#define IO_SUBCTRL_USB2_ARUSER_37_32_OFFSET 0

#define IO_SUBCTRL_USB2_ARUSER_95_64_LEN    32
#define IO_SUBCTRL_USB2_ARUSER_95_64_OFFSET 0

#define IO_SUBCTRL_USB2_ARUSER_103_96_LEN    8
#define IO_SUBCTRL_USB2_ARUSER_103_96_OFFSET 0

#define IO_SUBCTRL_USB2_AWUSER_31_0_LEN    32
#define IO_SUBCTRL_USB2_AWUSER_31_0_OFFSET 0

#define IO_SUBCTRL_USB2_AWUSER_63_49_LEN    15
#define IO_SUBCTRL_USB2_AWUSER_63_49_OFFSET 17
#define IO_SUBCTRL_USB2_AWUSER_48_46_LEN    3
#define IO_SUBCTRL_USB2_AWUSER_48_46_OFFSET 14
#define IO_SUBCTRL_USB2_AWUSER_45_39_LEN    7
#define IO_SUBCTRL_USB2_AWUSER_45_39_OFFSET 7
#define IO_SUBCTRL_USB2_AWUSER_NS_LEN       1
#define IO_SUBCTRL_USB2_AWUSER_NS_OFFSET    6
#define IO_SUBCTRL_USB2_AWUSER_37_32_LEN    6
#define IO_SUBCTRL_USB2_AWUSER_37_32_OFFSET 0

#define IO_SUBCTRL_USB2_AWUSER_95_64_LEN    32
#define IO_SUBCTRL_USB2_AWUSER_95_64_OFFSET 0

#define IO_SUBCTRL_USB2_AWUSER_103_96_LEN    8
#define IO_SUBCTRL_USB2_AWUSER_103_96_OFFSET 0

#define IO_SUBCTRL_USB3_ARUSER_31_0_LEN    32
#define IO_SUBCTRL_USB3_ARUSER_31_0_OFFSET 0

#define IO_SUBCTRL_USB3_ARUSER_63_49_LEN    15
#define IO_SUBCTRL_USB3_ARUSER_63_49_OFFSET 17
#define IO_SUBCTRL_USB3_ARUSER_48_46_LEN    3
#define IO_SUBCTRL_USB3_ARUSER_48_46_OFFSET 14
#define IO_SUBCTRL_USB3_ARUSER_45_39_LEN    7
#define IO_SUBCTRL_USB3_ARUSER_45_39_OFFSET 7
#define IO_SUBCTRL_USB3_ARUSER_NS_LEN       1
#define IO_SUBCTRL_USB3_ARUSER_NS_OFFSET    6
#define IO_SUBCTRL_USB3_ARUSER_37_32_LEN    6
#define IO_SUBCTRL_USB3_ARUSER_37_32_OFFSET 0

#define IO_SUBCTRL_USB3_ARUSER_95_64_LEN    32
#define IO_SUBCTRL_USB3_ARUSER_95_64_OFFSET 0

#define IO_SUBCTRL_USB3_ARUSER_103_96_LEN    8
#define IO_SUBCTRL_USB3_ARUSER_103_96_OFFSET 0

#define IO_SUBCTRL_USB3_AWUSER_31_0_LEN    32
#define IO_SUBCTRL_USB3_AWUSER_31_0_OFFSET 0

#define IO_SUBCTRL_USB3_AWUSER_63_49_LEN    15
#define IO_SUBCTRL_USB3_AWUSER_63_49_OFFSET 17
#define IO_SUBCTRL_USB3_AWUSER_48_46_LEN    3
#define IO_SUBCTRL_USB3_AWUSER_48_46_OFFSET 14
#define IO_SUBCTRL_USB3_AWUSER_45_39_LEN    7
#define IO_SUBCTRL_USB3_AWUSER_45_39_OFFSET 7
#define IO_SUBCTRL_USB3_AWUSER_NS_LEN       1
#define IO_SUBCTRL_USB3_AWUSER_NS_OFFSET    6
#define IO_SUBCTRL_USB3_AWUSER_37_32_LEN    6
#define IO_SUBCTRL_USB3_AWUSER_37_32_OFFSET 0

#define IO_SUBCTRL_USB3_AWUSER_95_64_LEN    32
#define IO_SUBCTRL_USB3_AWUSER_95_64_OFFSET 0

#define IO_SUBCTRL_USB3_AWUSER_103_96_LEN    8
#define IO_SUBCTRL_USB3_AWUSER_103_96_OFFSET 0

#define IO_SUBCTRL_USB_BRG1_DLOCK_CLR_LEN          1
#define IO_SUBCTRL_USB_BRG1_DLOCK_CLR_OFFSET       7
#define IO_SUBCTRL_USB_BRG1_SLV_PRIORITY_M1_LEN    1
#define IO_SUBCTRL_USB_BRG1_SLV_PRIORITY_M1_OFFSET 6
#define IO_SUBCTRL_USB_BRG1_MST_PRIORITY_M2_LEN    1
#define IO_SUBCTRL_USB_BRG1_MST_PRIORITY_M2_OFFSET 5
#define IO_SUBCTRL_USB_BRG1_MST_PRIORITY_M1_LEN    1
#define IO_SUBCTRL_USB_BRG1_MST_PRIORITY_M1_OFFSET 4
#define IO_SUBCTRL_USB_BRG0_DLOCK_CLR_LEN          1
#define IO_SUBCTRL_USB_BRG0_DLOCK_CLR_OFFSET       3
#define IO_SUBCTRL_USB_BRG0_SLV_PRIORITY_M1_LEN    1
#define IO_SUBCTRL_USB_BRG0_SLV_PRIORITY_M1_OFFSET 2
#define IO_SUBCTRL_USB_BRG0_MST_PRIORITY_M2_LEN    1
#define IO_SUBCTRL_USB_BRG0_MST_PRIORITY_M2_OFFSET 1
#define IO_SUBCTRL_USB_BRG0_MST_PRIORITY_M1_LEN    1
#define IO_SUBCTRL_USB_BRG0_MST_PRIORITY_M1_OFFSET 0

#define IO_SUBCTRL_USBC_POWERPRESENT_SEL_LEN    1
#define IO_SUBCTRL_USBC_POWERPRESENT_SEL_OFFSET 4
#define IO_SUBCTRL_USBC_POWERPRESENT_CFG_LEN    4
#define IO_SUBCTRL_USBC_POWERPRESENT_CFG_OFFSET 0

#define IO_SUBCTRL_USBC_VBUSVALID_SEL_LEN    1
#define IO_SUBCTRL_USBC_VBUSVALID_SEL_OFFSET 4
#define IO_SUBCTRL_USBC_VBUSVALID_CFG_LEN    4
#define IO_SUBCTRL_USBC_VBUSVALID_CFG_OFFSET 0

#define IO_SUBCTRL_USBC_POWEREN_SEL_LEN    1
#define IO_SUBCTRL_USBC_POWEREN_SEL_OFFSET 4
#define IO_SUBCTRL_USBC_POWEREN_CFG_LEN    4
#define IO_SUBCTRL_USBC_POWEREN_CFG_OFFSET 0

#define IO_SUBCTRL_USBC_PORT_OCA_POLARITY_SEL_LEN    1
#define IO_SUBCTRL_USBC_PORT_OCA_POLARITY_SEL_OFFSET 9
#define IO_SUBCTRL_USBC_PORT_OCA_SEL_LEN             1
#define IO_SUBCTRL_USBC_PORT_OCA_SEL_OFFSET          8
#define IO_SUBCTRL_USBC_PORT_OCA_CFG_LEN             8
#define IO_SUBCTRL_USBC_PORT_OCA_CFG_OFFSET          0

#define IO_SUBCTRL_USBC_LOGIC_TRACE_SEL_LEN    2
#define IO_SUBCTRL_USBC_LOGIC_TRACE_SEL_OFFSET 0

#define IO_SUBCTRL_PCIE_AXPROT_CFG_LEN    3
#define IO_SUBCTRL_PCIE_AXPROT_CFG_OFFSET 0

#define IO_SUBCTRL_NIC_AXPROT_CFG_LEN    3
#define IO_SUBCTRL_NIC_AXPROT_CFG_OFFSET 0

#define IO_SUBCTRL_DCDRERR_SECERR_SLVERR_VISERR_USBC0_LEN    4
#define IO_SUBCTRL_DCDRERR_SECERR_SLVERR_VISERR_USBC0_OFFSET 5
#define IO_SUBCTRL_DLOCK_AHB_USBC0_LEN                       3
#define IO_SUBCTRL_DLOCK_AHB_USBC0_OFFSET                    2
#define IO_SUBCTRL_DLOCK_MSTBUSY_USBC0_LEN                   2
#define IO_SUBCTRL_DLOCK_MSTBUSY_USBC0_OFFSET                0

#define IO_SUBCTRL_DBG_HADDR_USBC0_LEN    32
#define IO_SUBCTRL_DBG_HADDR_USBC0_OFFSET 0

#define IO_SUBCTRL_DBG_HWDATA_USBC0_LEN    32
#define IO_SUBCTRL_DBG_HWDATA_USBC0_OFFSET 0

#define IO_SUBCTRL_DBG_HRDATA_USBC0_LEN    32
#define IO_SUBCTRL_DBG_HRDATA_USBC0_OFFSET 0

#define IO_SUBCTRL_DBG_HBURST_USBC0_LEN       3
#define IO_SUBCTRL_DBG_HBURST_USBC0_OFFSET    19
#define IO_SUBCTRL_DBG_HEXCL_USBC0_LEN        1
#define IO_SUBCTRL_DBG_HEXCL_USBC0_OFFSET     18
#define IO_SUBCTRL_DBG_HEXOKAY_USBC0_LEN      1
#define IO_SUBCTRL_DBG_HEXOKAY_USBC0_OFFSET   17
#define IO_SUBCTRL_DBG_HEXT_SEL_USBC0_LEN     2
#define IO_SUBCTRL_DBG_HEXT_SEL_USBC0_OFFSET  15
#define IO_SUBCTRL_DBG_HMASTER_USBC0_LEN      1
#define IO_SUBCTRL_DBG_HMASTER_USBC0_OFFSET   14
#define IO_SUBCTRL_DBG_HMASTLOCK_USBC0_LEN    1
#define IO_SUBCTRL_DBG_HMASTLOCK_USBC0_OFFSET 13
#define IO_SUBCTRL_DBG_HNONSEC_USBC0_LEN      1
#define IO_SUBCTRL_DBG_HNONSEC_USBC0_OFFSET   12
#define IO_SUBCTRL_DBG_HPROT_USBC0_LEN        4
#define IO_SUBCTRL_DBG_HPROT_USBC0_OFFSET     8
#define IO_SUBCTRL_DBG_HRESP_USBC0_LEN        2
#define IO_SUBCTRL_DBG_HRESP_USBC0_OFFSET     6
#define IO_SUBCTRL_DBG_HSIZE_USBC0_LEN        3
#define IO_SUBCTRL_DBG_HSIZE_USBC0_OFFSET     3
#define IO_SUBCTRL_DBG_HTRANS_USBC0_LEN       2
#define IO_SUBCTRL_DBG_HTRANS_USBC0_OFFSET    1
#define IO_SUBCTRL_DBG_HWRITE_USBC0_LEN       1
#define IO_SUBCTRL_DBG_HWRITE_USBC0_OFFSET    0

#define IO_SUBCTRL_DCDRERR_SECERR_SLVERR_VISERR_USBC1_LEN    4
#define IO_SUBCTRL_DCDRERR_SECERR_SLVERR_VISERR_USBC1_OFFSET 5
#define IO_SUBCTRL_DLOCK_AHB_USBC1_LEN                       3
#define IO_SUBCTRL_DLOCK_AHB_USBC1_OFFSET                    2
#define IO_SUBCTRL_DLOCK_MSTBUSY_USBC1_LEN                   2
#define IO_SUBCTRL_DLOCK_MSTBUSY_USBC1_OFFSET                0

#define IO_SUBCTRL_DBG_HADDR_USBC1_LEN    32
#define IO_SUBCTRL_DBG_HADDR_USBC1_OFFSET 0

#define IO_SUBCTRL_DBG_HWDATA_USBC1_LEN    32
#define IO_SUBCTRL_DBG_HWDATA_USBC1_OFFSET 0

#define IO_SUBCTRL_DBG_HRDATA_USBC1_LEN    32
#define IO_SUBCTRL_DBG_HRDATA_USBC1_OFFSET 0

#define IO_SUBCTRL_DBG_HBURST_USBC1_LEN       3
#define IO_SUBCTRL_DBG_HBURST_USBC1_OFFSET    19
#define IO_SUBCTRL_DBG_HEXCL_USBC1_LEN        1
#define IO_SUBCTRL_DBG_HEXCL_USBC1_OFFSET     18
#define IO_SUBCTRL_DBG_HEXOKAY_USBC1_LEN      1
#define IO_SUBCTRL_DBG_HEXOKAY_USBC1_OFFSET   17
#define IO_SUBCTRL_DBG_HEXT_SEL_USBC1_LEN     2
#define IO_SUBCTRL_DBG_HEXT_SEL_USBC1_OFFSET  15
#define IO_SUBCTRL_DBG_HMASTER_USBC1_LEN      1
#define IO_SUBCTRL_DBG_HMASTER_USBC1_OFFSET   14
#define IO_SUBCTRL_DBG_HMASTLOCK_USBC1_LEN    1
#define IO_SUBCTRL_DBG_HMASTLOCK_USBC1_OFFSET 13
#define IO_SUBCTRL_DBG_HNONSEC_USBC1_LEN      1
#define IO_SUBCTRL_DBG_HNONSEC_USBC1_OFFSET   12
#define IO_SUBCTRL_DBG_HPROT_USBC1_LEN        4
#define IO_SUBCTRL_DBG_HPROT_USBC1_OFFSET     8
#define IO_SUBCTRL_DBG_HRESP_USBC1_LEN        2
#define IO_SUBCTRL_DBG_HRESP_USBC1_OFFSET     6
#define IO_SUBCTRL_DBG_HSIZE_USBC1_LEN        3
#define IO_SUBCTRL_DBG_HSIZE_USBC1_OFFSET     3
#define IO_SUBCTRL_DBG_HTRANS_USBC1_LEN       2
#define IO_SUBCTRL_DBG_HTRANS_USBC1_OFFSET    1
#define IO_SUBCTRL_DBG_HWRITE_USBC1_LEN       1
#define IO_SUBCTRL_DBG_HWRITE_USBC1_OFFSET    0

#define IO_SUBCTRL_DCDRERR_SECERR_SLVERR_VISERR_USBC2_LEN    4
#define IO_SUBCTRL_DCDRERR_SECERR_SLVERR_VISERR_USBC2_OFFSET 5
#define IO_SUBCTRL_DLOCK_AHB_USBC2_LEN                       3
#define IO_SUBCTRL_DLOCK_AHB_USBC2_OFFSET                    2
#define IO_SUBCTRL_DLOCK_MSTBUSY_USBC2_LEN                   2
#define IO_SUBCTRL_DLOCK_MSTBUSY_USBC2_OFFSET                0

#define IO_SUBCTRL_DBG_HADDR_USBC2_LEN    32
#define IO_SUBCTRL_DBG_HADDR_USBC2_OFFSET 0

#define IO_SUBCTRL_DBG_HWDATA_USBC2_LEN    32
#define IO_SUBCTRL_DBG_HWDATA_USBC2_OFFSET 0

#define IO_SUBCTRL_DBG_HRDATA_USBC2_LEN    32
#define IO_SUBCTRL_DBG_HRDATA_USBC2_OFFSET 0

#define IO_SUBCTRL_DBG_HBURST_USBC2_LEN       3
#define IO_SUBCTRL_DBG_HBURST_USBC2_OFFSET    19
#define IO_SUBCTRL_DBG_HEXCL_USBC2_LEN        1
#define IO_SUBCTRL_DBG_HEXCL_USBC2_OFFSET     18
#define IO_SUBCTRL_DBG_HEXOKAY_USBC2_LEN      1
#define IO_SUBCTRL_DBG_HEXOKAY_USBC2_OFFSET   17
#define IO_SUBCTRL_DBG_HEXT_SEL_USBC2_LEN     2
#define IO_SUBCTRL_DBG_HEXT_SEL_USBC2_OFFSET  15
#define IO_SUBCTRL_DBG_HMASTER_USBC2_LEN      1
#define IO_SUBCTRL_DBG_HMASTER_USBC2_OFFSET   14
#define IO_SUBCTRL_DBG_HMASTLOCK_USBC2_LEN    1
#define IO_SUBCTRL_DBG_HMASTLOCK_USBC2_OFFSET 13
#define IO_SUBCTRL_DBG_HNONSEC_USBC2_LEN      1
#define IO_SUBCTRL_DBG_HNONSEC_USBC2_OFFSET   12
#define IO_SUBCTRL_DBG_HPROT_USBC2_LEN        4
#define IO_SUBCTRL_DBG_HPROT_USBC2_OFFSET     8
#define IO_SUBCTRL_DBG_HRESP_USBC2_LEN        2
#define IO_SUBCTRL_DBG_HRESP_USBC2_OFFSET     6
#define IO_SUBCTRL_DBG_HSIZE_USBC2_LEN        3
#define IO_SUBCTRL_DBG_HSIZE_USBC2_OFFSET     3
#define IO_SUBCTRL_DBG_HTRANS_USBC2_LEN       2
#define IO_SUBCTRL_DBG_HTRANS_USBC2_OFFSET    1
#define IO_SUBCTRL_DBG_HWRITE_USBC2_LEN       1
#define IO_SUBCTRL_DBG_HWRITE_USBC2_OFFSET    0

#define IO_SUBCTRL_DCDRERR_SECERR_SLVERR_VISERR_USBC3_LEN    4
#define IO_SUBCTRL_DCDRERR_SECERR_SLVERR_VISERR_USBC3_OFFSET 5
#define IO_SUBCTRL_DLOCK_AHB_USBC3_LEN                       3
#define IO_SUBCTRL_DLOCK_AHB_USBC3_OFFSET                    2
#define IO_SUBCTRL_DLOCK_MSTBUSY_USBC3_LEN                   2
#define IO_SUBCTRL_DLOCK_MSTBUSY_USBC3_OFFSET                0

#define IO_SUBCTRL_DBG_HADDR_USBC3_LEN    32
#define IO_SUBCTRL_DBG_HADDR_USBC3_OFFSET 0

#define IO_SUBCTRL_DBG_HWDATA_USBC3_LEN    32
#define IO_SUBCTRL_DBG_HWDATA_USBC3_OFFSET 0

#define IO_SUBCTRL_DBG_HRDATA_USBC3_LEN    32
#define IO_SUBCTRL_DBG_HRDATA_USBC3_OFFSET 0

#define IO_SUBCTRL_DBG_HBURST_USBC3_LEN       3
#define IO_SUBCTRL_DBG_HBURST_USBC3_OFFSET    19
#define IO_SUBCTRL_DBG_HEXCL_USBC3_LEN        1
#define IO_SUBCTRL_DBG_HEXCL_USBC3_OFFSET     18
#define IO_SUBCTRL_DBG_HEXOKAY_USBC3_LEN      1
#define IO_SUBCTRL_DBG_HEXOKAY_USBC3_OFFSET   17
#define IO_SUBCTRL_DBG_HEXT_SEL_USBC3_LEN     2
#define IO_SUBCTRL_DBG_HEXT_SEL_USBC3_OFFSET  15
#define IO_SUBCTRL_DBG_HMASTER_USBC3_LEN      1
#define IO_SUBCTRL_DBG_HMASTER_USBC3_OFFSET   14
#define IO_SUBCTRL_DBG_HMASTLOCK_USBC3_LEN    1
#define IO_SUBCTRL_DBG_HMASTLOCK_USBC3_OFFSET 13
#define IO_SUBCTRL_DBG_HNONSEC_USBC3_LEN      1
#define IO_SUBCTRL_DBG_HNONSEC_USBC3_OFFSET   12
#define IO_SUBCTRL_DBG_HPROT_USBC3_LEN        4
#define IO_SUBCTRL_DBG_HPROT_USBC3_OFFSET     8
#define IO_SUBCTRL_DBG_HRESP_USBC3_LEN        2
#define IO_SUBCTRL_DBG_HRESP_USBC3_OFFSET     6
#define IO_SUBCTRL_DBG_HSIZE_USBC3_LEN        3
#define IO_SUBCTRL_DBG_HSIZE_USBC3_OFFSET     3
#define IO_SUBCTRL_DBG_HTRANS_USBC3_LEN       2
#define IO_SUBCTRL_DBG_HTRANS_USBC3_OFFSET    1
#define IO_SUBCTRL_DBG_HWRITE_USBC3_LEN       1
#define IO_SUBCTRL_DBG_HWRITE_USBC3_OFFSET    0

#define IO_SUBCTRL_XXVGE_TX_CLK_SEL_LEN    4
#define IO_SUBCTRL_XXVGE_TX_CLK_SEL_OFFSET 4
#define IO_SUBCTRL_XXVGE_RX_CLK_SEL_LEN    4
#define IO_SUBCTRL_XXVGE_RX_CLK_SEL_OFFSET 0

#define IO_SUBCTRL_RGMII_TX_MODE_LEN    4
#define IO_SUBCTRL_RGMII_TX_MODE_OFFSET 0

#define IO_SUBCTRL_INT_INJECT_EN_LEN    1
#define IO_SUBCTRL_INT_INJECT_EN_OFFSET 0

#define IO_SUBCTRL_NIC_AXUSER_CMD_TYPE_LEN    12
#define IO_SUBCTRL_NIC_AXUSER_CMD_TYPE_OFFSET 0

#define IO_SUBCTRL_HILINK_GE_LOS_SEL_LEN    2
#define IO_SUBCTRL_HILINK_GE_LOS_SEL_OFFSET 0

#define IO_SUBCTRL_HILINK_USB_GE_DIV_MODE_LEN    4
#define IO_SUBCTRL_HILINK_USB_GE_DIV_MODE_OFFSET 0

#define IO_SUBCTRL_EPHY0_RST_CTRL_OUT_LEN    1
#define IO_SUBCTRL_EPHY0_RST_CTRL_OUT_OFFSET 1
#define IO_SUBCTRL_EPHY1_RST_CTRL_OUT_LEN    1
#define IO_SUBCTRL_EPHY1_RST_CTRL_OUT_OFFSET 0

#define IO_SUBCTRL_TSENSOR_TIMEOUT_OVER_LEN    1
#define IO_SUBCTRL_TSENSOR_TIMEOUT_OVER_OFFSET 3
#define IO_SUBCTRL_TSENSOR_ULTRAOVER_LEN       1
#define IO_SUBCTRL_TSENSOR_ULTRAOVER_OFFSET    2
#define IO_SUBCTRL_TSENSOR_OVER_LEN            1
#define IO_SUBCTRL_TSENSOR_OVER_OFFSET         1
#define IO_SUBCTRL_TSENSOR_UNDER_LEN           1
#define IO_SUBCTRL_TSENSOR_UNDER_OFFSET        0

#define IO_SUBCTRL_TSENSOR_TIMEOUT_MASK_LEN          1
#define IO_SUBCTRL_TSENSOR_TIMEOUT_MASK_OFFSET       3
#define IO_SUBCTRL_TSENSOR_ULTRAOVER_INT_MASK_LEN    1
#define IO_SUBCTRL_TSENSOR_ULTRAOVER_INT_MASK_OFFSET 2
#define IO_SUBCTRL_TSENSOR_OVER_INT_MASK_LEN         1
#define IO_SUBCTRL_TSENSOR_OVER_INT_MASK_OFFSET      1
#define IO_SUBCTRL_TSENSOR_UNDER_INT_MASK_LEN        1
#define IO_SUBCTRL_TSENSOR_UNDER_INT_MASK_OFFSET     0

#define IO_SUBCTRL_OOO_ECC_MULTPL_INTMASK0_LEN    1
#define IO_SUBCTRL_OOO_ECC_MULTPL_INTMASK0_OFFSET 1
#define IO_SUBCTRL_OOO_ECC_DECT_INTMASK0_LEN      1
#define IO_SUBCTRL_OOO_ECC_DECT_INTMASK0_OFFSET   0

#define IO_SUBCTRL_OOO_ECC_MULTPL_RAW0_LEN    1
#define IO_SUBCTRL_OOO_ECC_MULTPL_RAW0_OFFSET 1
#define IO_SUBCTRL_OOO_ECC_DECT_RAW0_LEN      1
#define IO_SUBCTRL_OOO_ECC_DECT_RAW0_OFFSET   0

#define IO_SUBCTRL_OOO_ECC_MULTPL_INT0_LEN    1
#define IO_SUBCTRL_OOO_ECC_MULTPL_INT0_OFFSET 1
#define IO_SUBCTRL_OOO_ECC_DECT_INT0_LEN      1
#define IO_SUBCTRL_OOO_ECC_DECT_INT0_OFFSET   0

#define IO_SUBCTRL_OOO_ECC_MULTPL_INTMASK1_LEN    1
#define IO_SUBCTRL_OOO_ECC_MULTPL_INTMASK1_OFFSET 1
#define IO_SUBCTRL_OOO_ECC_DECT_INTMASK1_LEN      1
#define IO_SUBCTRL_OOO_ECC_DECT_INTMASK1_OFFSET   0

#define IO_SUBCTRL_OOO_ECC_MULTPL_RAW1_LEN    1
#define IO_SUBCTRL_OOO_ECC_MULTPL_RAW1_OFFSET 1
#define IO_SUBCTRL_OOO_ECC_DECT_RAW1_LEN      1
#define IO_SUBCTRL_OOO_ECC_DECT_RAW1_OFFSET   0

#define IO_SUBCTRL_OOO_ECC_MULTPL_INT1_LEN    1
#define IO_SUBCTRL_OOO_ECC_MULTPL_INT1_OFFSET 1
#define IO_SUBCTRL_OOO_ECC_DECT_INT1_LEN      1
#define IO_SUBCTRL_OOO_ECC_DECT_INT1_OFFSET   0

#define IO_SUBCTRL_ICG_ST_SMMU_TCU_LEN    1
#define IO_SUBCTRL_ICG_ST_SMMU_TCU_OFFSET 1
#define IO_SUBCTRL_ICG_ST_SMMU_TBU_LEN    1
#define IO_SUBCTRL_ICG_ST_SMMU_TBU_OFFSET 0

#define IO_SUBCTRL_ICG_ST_GPIO_DB_LEN    1
#define IO_SUBCTRL_ICG_ST_GPIO_DB_OFFSET 2
#define IO_SUBCTRL_ICG_ST_GPIO_LEN       2
#define IO_SUBCTRL_ICG_ST_GPIO_OFFSET    0

#define IO_SUBCTRL_ICG_ST_APB_IO_MUX_LEN    1
#define IO_SUBCTRL_ICG_ST_APB_IO_MUX_OFFSET 0

#define IO_SUBCTRL_ICG_ST_PROBE_LEN    1
#define IO_SUBCTRL_ICG_ST_PROBE_OFFSET 0

#define IO_SUBCTRL_ICG_ST_MDIO_LEN    2
#define IO_SUBCTRL_ICG_ST_MDIO_OFFSET 0

#define IO_SUBCTRL_ICG_ST_HILINK0_PMA_RX_LEN    4
#define IO_SUBCTRL_ICG_ST_HILINK0_PMA_RX_OFFSET 10
#define IO_SUBCTRL_ICG_ST_HILINK0_PMA_TX_LEN    4
#define IO_SUBCTRL_ICG_ST_HILINK0_PMA_TX_OFFSET 6
#define IO_SUBCTRL_ICG_ST_HILINK0_RXOCLK_LEN    4
#define IO_SUBCTRL_ICG_ST_HILINK0_RXOCLK_OFFSET 2
#define IO_SUBCTRL_ICG_ST_HILINK0_MCLK_LEN      2
#define IO_SUBCTRL_ICG_ST_HILINK0_MCLK_OFFSET   0

#define IO_SUBCTRL_ICG_ST_HILINK1_PMA_RX_LEN    4
#define IO_SUBCTRL_ICG_ST_HILINK1_PMA_RX_OFFSET 10
#define IO_SUBCTRL_ICG_ST_HILINK1_PMA_TX_LEN    4
#define IO_SUBCTRL_ICG_ST_HILINK1_PMA_TX_OFFSET 6
#define IO_SUBCTRL_ICG_ST_HILINK1_RXOCLK_LEN    4
#define IO_SUBCTRL_ICG_ST_HILINK1_RXOCLK_OFFSET 2
#define IO_SUBCTRL_ICG_ST_HILINK1_MCLK_LEN      2
#define IO_SUBCTRL_ICG_ST_HILINK1_MCLK_OFFSET   0

#define IO_SUBCTRL_ICG_ST_SDS_SYS_CLK_LEN    2
#define IO_SUBCTRL_ICG_ST_SDS_SYS_CLK_OFFSET 0

#define IO_SUBCTRL_ICG_ST_PCIE_SLV_LEN    1
#define IO_SUBCTRL_ICG_ST_PCIE_SLV_OFFSET 1
#define IO_SUBCTRL_ICG_ST_PCIE_MST_LEN    1
#define IO_SUBCTRL_ICG_ST_PCIE_MST_OFFSET 0

#define IO_SUBCTRL_ICG_ST_PCIE0_CLK_TL_AXI_LEN           1
#define IO_SUBCTRL_ICG_ST_PCIE0_CLK_TL_AXI_OFFSET        31
#define IO_SUBCTRL_ICG_ST_PCIE0_CLK_AP_AXI_LEN           5
#define IO_SUBCTRL_ICG_ST_PCIE0_CLK_AP_AXI_OFFSET        26
#define IO_SUBCTRL_ICG_ST_PCIE0_CLK_APB_LEN              2
#define IO_SUBCTRL_ICG_ST_PCIE0_CLK_APB_OFFSET           24
#define IO_SUBCTRL_ICG_ST_PCIE0_CLK_CORE_PHY_LANE_LEN    4
#define IO_SUBCTRL_ICG_ST_PCIE0_CLK_CORE_PHY_LANE_OFFSET 20
#define IO_SUBCTRL_ICG_ST_PCIE0_CLK_PCS_LOGIC_LEN        4
#define IO_SUBCTRL_ICG_ST_PCIE0_CLK_PCS_LOGIC_OFFSET     16
#define IO_SUBCTRL_ICG_ST_PCIE0_CLK_PCS_LOGIC_DIV_LEN    4
#define IO_SUBCTRL_ICG_ST_PCIE0_CLK_PCS_LOGIC_DIV_OFFSET 12
#define IO_SUBCTRL_ICG_ST_PCIE0_CLK_PCS_RX_LEN           4
#define IO_SUBCTRL_ICG_ST_PCIE0_CLK_PCS_RX_OFFSET        8
#define IO_SUBCTRL_ICG_ST_PCIE0_CLK_PCS_TX_LEN           4
#define IO_SUBCTRL_ICG_ST_PCIE0_CLK_PCS_TX_OFFSET        4
#define IO_SUBCTRL_ICG_ST_PCIE0_CLK_PIPE_LANE_LEN        4
#define IO_SUBCTRL_ICG_ST_PCIE0_CLK_PIPE_LANE_OFFSET     0

#define IO_SUBCTRL_ICG_ST_PCIE0_CLK_CORE_PHY_COMMON_LEN      1
#define IO_SUBCTRL_ICG_ST_PCIE0_CLK_CORE_PHY_COMMON_OFFSET   7
#define IO_SUBCTRL_ICG_ST_PCIE0_CLK_CORE_PHY_PORT_LEN        1
#define IO_SUBCTRL_ICG_ST_PCIE0_CLK_CORE_PHY_PORT_OFFSET     6
#define IO_SUBCTRL_ICG_ST_PCIE0_CLK_CORE_PHY_PORT_DIV_LEN    1
#define IO_SUBCTRL_ICG_ST_PCIE0_CLK_CORE_PHY_PORT_DIV_OFFSET 5
#define IO_SUBCTRL_ICG_ST_PCIE0_CLK_CORE_TL_COMMON_LEN       1
#define IO_SUBCTRL_ICG_ST_PCIE0_CLK_CORE_TL_COMMON_OFFSET    4
#define IO_SUBCTRL_ICG_ST_PCIE0_CLK_CORE_TL_PORT_LEN         1
#define IO_SUBCTRL_ICG_ST_PCIE0_CLK_CORE_TL_PORT_OFFSET      3
#define IO_SUBCTRL_ICG_ST_PCIE0_CLK_CORE_TL_PORT_DIV_LEN     1
#define IO_SUBCTRL_ICG_ST_PCIE0_CLK_CORE_TL_PORT_DIV_OFFSET  2
#define IO_SUBCTRL_ICG_ST_PCIE0_CLK_PCS_APB_LEN              1
#define IO_SUBCTRL_ICG_ST_PCIE0_CLK_PCS_APB_OFFSET           1
#define IO_SUBCTRL_ICG_ST_PCIE0_CLK_PCS_LOGIC_COMMON_LEN     1
#define IO_SUBCTRL_ICG_ST_PCIE0_CLK_PCS_LOGIC_COMMON_OFFSET  0

#define IO_SUBCTRL_ICG_ST_PCIE1_CLK_TL_AXI_LEN           1
#define IO_SUBCTRL_ICG_ST_PCIE1_CLK_TL_AXI_OFFSET        31
#define IO_SUBCTRL_ICG_ST_PCIE1_CLK_AP_AXI_LEN           5
#define IO_SUBCTRL_ICG_ST_PCIE1_CLK_AP_AXI_OFFSET        26
#define IO_SUBCTRL_ICG_ST_PCIE1_CLK_APB_LEN              2
#define IO_SUBCTRL_ICG_ST_PCIE1_CLK_APB_OFFSET           24
#define IO_SUBCTRL_ICG_ST_PCIE1_CLK_CORE_PHY_LANE_LEN    4
#define IO_SUBCTRL_ICG_ST_PCIE1_CLK_CORE_PHY_LANE_OFFSET 20
#define IO_SUBCTRL_ICG_ST_PCIE1_CLK_PCS_LOGIC_LEN        4
#define IO_SUBCTRL_ICG_ST_PCIE1_CLK_PCS_LOGIC_OFFSET     16
#define IO_SUBCTRL_ICG_ST_PCIE1_CLK_PCS_LOGIC_DIV_LEN    4
#define IO_SUBCTRL_ICG_ST_PCIE1_CLK_PCS_LOGIC_DIV_OFFSET 12
#define IO_SUBCTRL_ICG_ST_PCIE1_CLK_PCS_RX_LEN           4
#define IO_SUBCTRL_ICG_ST_PCIE1_CLK_PCS_RX_OFFSET        8
#define IO_SUBCTRL_ICG_ST_PCIE1_CLK_PCS_TX_LEN           4
#define IO_SUBCTRL_ICG_ST_PCIE1_CLK_PCS_TX_OFFSET        4
#define IO_SUBCTRL_ICG_ST_PCIE1_CLK_PIPE_LANE_LEN        4
#define IO_SUBCTRL_ICG_ST_PCIE1_CLK_PIPE_LANE_OFFSET     0

#define IO_SUBCTRL_ICG_ST_PCIE1_CLK_CORE_PHY_COMMON_LEN      1
#define IO_SUBCTRL_ICG_ST_PCIE1_CLK_CORE_PHY_COMMON_OFFSET   7
#define IO_SUBCTRL_ICG_ST_PCIE1_CLK_CORE_PHY_PORT_LEN        1
#define IO_SUBCTRL_ICG_ST_PCIE1_CLK_CORE_PHY_PORT_OFFSET     6
#define IO_SUBCTRL_ICG_ST_PCIE1_CLK_CORE_PHY_PORT_DIV_LEN    1
#define IO_SUBCTRL_ICG_ST_PCIE1_CLK_CORE_PHY_PORT_DIV_OFFSET 5
#define IO_SUBCTRL_ICG_ST_PCIE1_CLK_CORE_TL_COMMON_LEN       1
#define IO_SUBCTRL_ICG_ST_PCIE1_CLK_CORE_TL_COMMON_OFFSET    4
#define IO_SUBCTRL_ICG_ST_PCIE1_CLK_CORE_TL_PORT_LEN         1
#define IO_SUBCTRL_ICG_ST_PCIE1_CLK_CORE_TL_PORT_OFFSET      3
#define IO_SUBCTRL_ICG_ST_PCIE1_CLK_CORE_TL_PORT_DIV_LEN     1
#define IO_SUBCTRL_ICG_ST_PCIE1_CLK_CORE_TL_PORT_DIV_OFFSET  2
#define IO_SUBCTRL_ICG_ST_PCIE1_CLK_PCS_APB_LEN              1
#define IO_SUBCTRL_ICG_ST_PCIE1_CLK_PCS_APB_OFFSET           1
#define IO_SUBCTRL_ICG_ST_PCIE1_CLK_PCS_LOGIC_COMMON_LEN     1
#define IO_SUBCTRL_ICG_ST_PCIE1_CLK_PCS_LOGIC_COMMON_OFFSET  0

#define IO_SUBCTRL_ICG_ST_PCIE2_CLK_TL_AXI_LEN           1
#define IO_SUBCTRL_ICG_ST_PCIE2_CLK_TL_AXI_OFFSET        31
#define IO_SUBCTRL_ICG_ST_PCIE2_CLK_AP_AXI_LEN           5
#define IO_SUBCTRL_ICG_ST_PCIE2_CLK_AP_AXI_OFFSET        26
#define IO_SUBCTRL_ICG_ST_PCIE2_CLK_APB_LEN              2
#define IO_SUBCTRL_ICG_ST_PCIE2_CLK_APB_OFFSET           24
#define IO_SUBCTRL_ICG_ST_PCIE2_CLK_CORE_PHY_LANE_LEN    4
#define IO_SUBCTRL_ICG_ST_PCIE2_CLK_CORE_PHY_LANE_OFFSET 20
#define IO_SUBCTRL_ICG_ST_PCIE2_CLK_PCS_LOGIC_LEN        4
#define IO_SUBCTRL_ICG_ST_PCIE2_CLK_PCS_LOGIC_OFFSET     16
#define IO_SUBCTRL_ICG_ST_PCIE2_CLK_PCS_LOGIC_DIV_LEN    4
#define IO_SUBCTRL_ICG_ST_PCIE2_CLK_PCS_LOGIC_DIV_OFFSET 12
#define IO_SUBCTRL_ICG_ST_PCIE2_CLK_PCS_RX_LEN           4
#define IO_SUBCTRL_ICG_ST_PCIE2_CLK_PCS_RX_OFFSET        8
#define IO_SUBCTRL_ICG_ST_PCIE2_CLK_PCS_TX_LEN           4
#define IO_SUBCTRL_ICG_ST_PCIE2_CLK_PCS_TX_OFFSET        4
#define IO_SUBCTRL_ICG_ST_PCIE2_CLK_PIPE_LANE_LEN        4
#define IO_SUBCTRL_ICG_ST_PCIE2_CLK_PIPE_LANE_OFFSET     0

#define IO_SUBCTRL_ICG_ST_PCIE2_CLK_CORE_PHY_COMMON_LEN      1
#define IO_SUBCTRL_ICG_ST_PCIE2_CLK_CORE_PHY_COMMON_OFFSET   7
#define IO_SUBCTRL_ICG_ST_PCIE2_CLK_CORE_PHY_PORT_LEN        1
#define IO_SUBCTRL_ICG_ST_PCIE2_CLK_CORE_PHY_PORT_OFFSET     6
#define IO_SUBCTRL_ICG_ST_PCIE2_CLK_CORE_PHY_PORT_DIV_LEN    1
#define IO_SUBCTRL_ICG_ST_PCIE2_CLK_CORE_PHY_PORT_DIV_OFFSET 5
#define IO_SUBCTRL_ICG_ST_PCIE2_CLK_CORE_TL_COMMON_LEN       1
#define IO_SUBCTRL_ICG_ST_PCIE2_CLK_CORE_TL_COMMON_OFFSET    4
#define IO_SUBCTRL_ICG_ST_PCIE2_CLK_CORE_TL_PORT_LEN         1
#define IO_SUBCTRL_ICG_ST_PCIE2_CLK_CORE_TL_PORT_OFFSET      3
#define IO_SUBCTRL_ICG_ST_PCIE2_CLK_CORE_TL_PORT_DIV_LEN     1
#define IO_SUBCTRL_ICG_ST_PCIE2_CLK_CORE_TL_PORT_DIV_OFFSET  2
#define IO_SUBCTRL_ICG_ST_PCIE2_CLK_PCS_APB_LEN              1
#define IO_SUBCTRL_ICG_ST_PCIE2_CLK_PCS_APB_OFFSET           1
#define IO_SUBCTRL_ICG_ST_PCIE2_CLK_PCS_LOGIC_COMMON_LEN     1
#define IO_SUBCTRL_ICG_ST_PCIE2_CLK_PCS_LOGIC_COMMON_OFFSET  0

#define IO_SUBCTRL_ICG_ST_PCIE3_CLK_TL_AXI_LEN           1
#define IO_SUBCTRL_ICG_ST_PCIE3_CLK_TL_AXI_OFFSET        31
#define IO_SUBCTRL_ICG_ST_PCIE3_CLK_AP_AXI_LEN           5
#define IO_SUBCTRL_ICG_ST_PCIE3_CLK_AP_AXI_OFFSET        26
#define IO_SUBCTRL_ICG_ST_PCIE3_CLK_APB_LEN              2
#define IO_SUBCTRL_ICG_ST_PCIE3_CLK_APB_OFFSET           24
#define IO_SUBCTRL_ICG_ST_PCIE3_CLK_CORE_PHY_LANE_LEN    4
#define IO_SUBCTRL_ICG_ST_PCIE3_CLK_CORE_PHY_LANE_OFFSET 20
#define IO_SUBCTRL_ICG_ST_PCIE3_CLK_PCS_LOGIC_LEN        4
#define IO_SUBCTRL_ICG_ST_PCIE3_CLK_PCS_LOGIC_OFFSET     16
#define IO_SUBCTRL_ICG_ST_PCIE3_CLK_PCS_LOGIC_DIV_LEN    4
#define IO_SUBCTRL_ICG_ST_PCIE3_CLK_PCS_LOGIC_DIV_OFFSET 12
#define IO_SUBCTRL_ICG_ST_PCIE3_CLK_PCS_RX_LEN           4
#define IO_SUBCTRL_ICG_ST_PCIE3_CLK_PCS_RX_OFFSET        8
#define IO_SUBCTRL_ICG_ST_PCIE3_CLK_PCS_TX_LEN           4
#define IO_SUBCTRL_ICG_ST_PCIE3_CLK_PCS_TX_OFFSET        4
#define IO_SUBCTRL_ICG_ST_PCIE3_CLK_PIPE_LANE_LEN        4
#define IO_SUBCTRL_ICG_ST_PCIE3_CLK_PIPE_LANE_OFFSET     0

#define IO_SUBCTRL_ICG_ST_PCIE3_CLK_CORE_PHY_COMMON_LEN      1
#define IO_SUBCTRL_ICG_ST_PCIE3_CLK_CORE_PHY_COMMON_OFFSET   7
#define IO_SUBCTRL_ICG_ST_PCIE3_CLK_CORE_PHY_PORT_LEN        1
#define IO_SUBCTRL_ICG_ST_PCIE3_CLK_CORE_PHY_PORT_OFFSET     6
#define IO_SUBCTRL_ICG_ST_PCIE3_CLK_CORE_PHY_PORT_DIV_LEN    1
#define IO_SUBCTRL_ICG_ST_PCIE3_CLK_CORE_PHY_PORT_DIV_OFFSET 5
#define IO_SUBCTRL_ICG_ST_PCIE3_CLK_CORE_TL_COMMON_LEN       1
#define IO_SUBCTRL_ICG_ST_PCIE3_CLK_CORE_TL_COMMON_OFFSET    4
#define IO_SUBCTRL_ICG_ST_PCIE3_CLK_CORE_TL_PORT_LEN         1
#define IO_SUBCTRL_ICG_ST_PCIE3_CLK_CORE_TL_PORT_OFFSET      3
#define IO_SUBCTRL_ICG_ST_PCIE3_CLK_CORE_TL_PORT_DIV_LEN     1
#define IO_SUBCTRL_ICG_ST_PCIE3_CLK_CORE_TL_PORT_DIV_OFFSET  2
#define IO_SUBCTRL_ICG_ST_PCIE3_CLK_PCS_APB_LEN              1
#define IO_SUBCTRL_ICG_ST_PCIE3_CLK_PCS_APB_OFFSET           1
#define IO_SUBCTRL_ICG_ST_PCIE3_CLK_PCS_LOGIC_COMMON_LEN     1
#define IO_SUBCTRL_ICG_ST_PCIE3_CLK_PCS_LOGIC_COMMON_OFFSET  0

#define IO_SUBCTRL_ICG_ST_USBC_SYS_LEN    4
#define IO_SUBCTRL_ICG_ST_USBC_SYS_OFFSET 0

#define IO_SUBCTRL_ICG_ST_SATA_OOB_LEN    1
#define IO_SUBCTRL_ICG_ST_SATA_OOB_OFFSET 10
#define IO_SUBCTRL_ICG_ST_SATA_AXI_LEN    1
#define IO_SUBCTRL_ICG_ST_SATA_AXI_OFFSET 9
#define IO_SUBCTRL_ICG_ST_SATA_AHB_LEN    1
#define IO_SUBCTRL_ICG_ST_SATA_AHB_OFFSET 8
#define IO_SUBCTRL_ICG_ST_SATA_RX_LEN     4
#define IO_SUBCTRL_ICG_ST_SATA_RX_OFFSET  4
#define IO_SUBCTRL_ICG_ST_SATA_TX_LEN     4
#define IO_SUBCTRL_ICG_ST_SATA_TX_OFFSET  0

#define IO_SUBCTRL_ICG_ST_NIC_RGMII_RX_INV_LEN    2
#define IO_SUBCTRL_ICG_ST_NIC_RGMII_RX_INV_OFFSET 30
#define IO_SUBCTRL_ICG_ST_NIC_RGMII_RX_LEN        2
#define IO_SUBCTRL_ICG_ST_NIC_RGMII_RX_OFFSET     28
#define IO_SUBCTRL_ICG_ST_NIC_RGMII_TX_INV_LEN    2
#define IO_SUBCTRL_ICG_ST_NIC_RGMII_TX_INV_OFFSET 26
#define IO_SUBCTRL_ICG_ST_NIC_RGMII_TX_LEN        2
#define IO_SUBCTRL_ICG_ST_NIC_RGMII_TX_OFFSET     24
#define IO_SUBCTRL_ICG_ST_NIC_XXVGE_RX_SDS_LEN    4
#define IO_SUBCTRL_ICG_ST_NIC_XXVGE_RX_SDS_OFFSET 20
#define IO_SUBCTRL_ICG_ST_NIC_XXVGE_TX_SDS_LEN    4
#define IO_SUBCTRL_ICG_ST_NIC_XXVGE_TX_SDS_OFFSET 16
#define IO_SUBCTRL_ICG_ST_NIC_XXVGE_CORE_LEN      4
#define IO_SUBCTRL_ICG_ST_NIC_XXVGE_CORE_OFFSET   12
#define IO_SUBCTRL_ICG_ST_NIC_XXVGE_CFG_LEN       4
#define IO_SUBCTRL_ICG_ST_NIC_XXVGE_CFG_OFFSET    8
#define IO_SUBCTRL_ICG_ST_NIC_XXVGE_PTP_LEN       4
#define IO_SUBCTRL_ICG_ST_NIC_XXVGE_PTP_OFFSET    4
#define IO_SUBCTRL_ICG_ST_NIC_PTP_LEN             4
#define IO_SUBCTRL_ICG_ST_NIC_PTP_OFFSET          0

#define IO_SUBCTRL_ICG_ST_NIC_MAG_APP_LEN    1
#define IO_SUBCTRL_ICG_ST_NIC_MAG_APP_OFFSET 4
#define IO_SUBCTRL_ICG_ST_NIC_MAG_CFG_LEN    1
#define IO_SUBCTRL_ICG_ST_NIC_MAG_CFG_OFFSET 3
#define IO_SUBCTRL_ICG_ST_NIC_SLV_LEN        1
#define IO_SUBCTRL_ICG_ST_NIC_SLV_OFFSET     2
#define IO_SUBCTRL_ICG_ST_NIC_COMMON_LEN     1
#define IO_SUBCTRL_ICG_ST_NIC_COMMON_OFFSET  1
#define IO_SUBCTRL_ICG_ST_NIC_PPE_LEN        1
#define IO_SUBCTRL_ICG_ST_NIC_PPE_OFFSET     0

#define IO_SUBCTRL_ICG_ST_RGMII_RX_LEN        2
#define IO_SUBCTRL_ICG_ST_RGMII_RX_OFFSET     6
#define IO_SUBCTRL_ICG_ST_RGMII_RX_INV_LEN    2
#define IO_SUBCTRL_ICG_ST_RGMII_RX_INV_OFFSET 4
#define IO_SUBCTRL_ICG_ST_RGMII_TX_LEN        2
#define IO_SUBCTRL_ICG_ST_RGMII_TX_OFFSET     2
#define IO_SUBCTRL_ICG_ST_RGMII_TX_INV_LEN    2
#define IO_SUBCTRL_ICG_ST_RGMII_TX_INV_OFFSET 0

#define IO_SUBCTRL_ICG_ST_HPM_LEN    1
#define IO_SUBCTRL_ICG_ST_HPM_OFFSET 0

#define IO_SUBCTRL_ICG_ST_SENSOR_SAMP_LEN    1
#define IO_SUBCTRL_ICG_ST_SENSOR_SAMP_OFFSET 1
#define IO_SUBCTRL_ICG_ST_SENSOR_LEN         1
#define IO_SUBCTRL_ICG_ST_SENSOR_OFFSET      0

#define IO_SUBCTRL_ICG_ST_HILINK1_SRAM1_LEN    1
#define IO_SUBCTRL_ICG_ST_HILINK1_SRAM1_OFFSET 3
#define IO_SUBCTRL_ICG_ST_HILINK1_SRAM0_LEN    1
#define IO_SUBCTRL_ICG_ST_HILINK1_SRAM0_OFFSET 2
#define IO_SUBCTRL_ICG_ST_HILINK0_SRAM1_LEN    1
#define IO_SUBCTRL_ICG_ST_HILINK0_SRAM1_OFFSET 1
#define IO_SUBCTRL_ICG_ST_HILINK0_SRAM0_LEN    1
#define IO_SUBCTRL_ICG_ST_HILINK0_SRAM0_OFFSET 0

#define IO_SUBCTRL_ICG_ST_BCBIST0_LEN    1
#define IO_SUBCTRL_ICG_ST_BCBIST0_OFFSET 0

#define IO_SUBCTRL_SRST_ST_GPIO_LEN    2
#define IO_SUBCTRL_SRST_ST_GPIO_OFFSET 0

#define IO_SUBCTRL_SRST_ST_APB_IO_MUX_LEN    1
#define IO_SUBCTRL_SRST_ST_APB_IO_MUX_OFFSET 0

#define IO_SUBCTRL_SRST_ST_MDIO_LEN    2
#define IO_SUBCTRL_SRST_ST_MDIO_OFFSET 0

#define IO_SUBCTRL_SRST_ST_HILINK0_PMA_RX_LEN    4
#define IO_SUBCTRL_SRST_ST_HILINK0_PMA_RX_OFFSET 4
#define IO_SUBCTRL_SRST_ST_HILINK0_PMA_TX_LEN    4
#define IO_SUBCTRL_SRST_ST_HILINK0_PMA_TX_OFFSET 0

#define IO_SUBCTRL_SRST_ST_HILINK1_PMA_RX_LEN    4
#define IO_SUBCTRL_SRST_ST_HILINK1_PMA_RX_OFFSET 4
#define IO_SUBCTRL_SRST_ST_HILINK1_PMA_TX_LEN    4
#define IO_SUBCTRL_SRST_ST_HILINK1_PMA_TX_OFFSET 0

#define IO_SUBCTRL_SRST_ST_SDS_SDPI_LEN    2
#define IO_SUBCTRL_SRST_ST_SDS_SDPI_OFFSET 4
#define IO_SUBCTRL_SRST_ST_ADAP_LEN        4
#define IO_SUBCTRL_SRST_ST_ADAP_OFFSET     0

#define IO_SUBCTRL_SRST_ST_USBC_SYS_LEN        4
#define IO_SUBCTRL_SRST_ST_USBC_SYS_OFFSET     8
#define IO_SUBCTRL_SRST_ST_USBC_SUSPEND_LEN    4
#define IO_SUBCTRL_SRST_ST_USBC_SUSPEND_OFFSET 4
#define IO_SUBCTRL_SRST_ST_USBC_REF_LEN        4
#define IO_SUBCTRL_SRST_ST_USBC_REF_OFFSET     0

#define IO_SUBCTRL_SRST_ST_PHY_LEN    3
#define IO_SUBCTRL_SRST_ST_PHY_OFFSET 0

#define IO_SUBCTRL_SRST_ST_SATA_OOB_LEN    1
#define IO_SUBCTRL_SRST_ST_SATA_OOB_OFFSET 10
#define IO_SUBCTRL_SRST_ST_SATA_AXI_LEN    1
#define IO_SUBCTRL_SRST_ST_SATA_AXI_OFFSET 9
#define IO_SUBCTRL_SRST_ST_SATA_AHB_LEN    1
#define IO_SUBCTRL_SRST_ST_SATA_AHB_OFFSET 8
#define IO_SUBCTRL_SRST_ST_SATA_RX_LEN     4
#define IO_SUBCTRL_SRST_ST_SATA_RX_OFFSET  4
#define IO_SUBCTRL_SRST_ST_SATA_TX_LEN     4
#define IO_SUBCTRL_SRST_ST_SATA_TX_OFFSET  0

#define IO_SUBCTRL_SRST_ST_NIC_RGMII_RX_INV_LEN       2
#define IO_SUBCTRL_SRST_ST_NIC_RGMII_RX_INV_OFFSET    30
#define IO_SUBCTRL_SRST_ST_NIC_RGMII_RX_LEN           2
#define IO_SUBCTRL_SRST_ST_NIC_RGMII_RX_OFFSET        28
#define IO_SUBCTRL_SRST_ST_NIC_RGMII_TX_INV_LEN       2
#define IO_SUBCTRL_SRST_ST_NIC_RGMII_TX_INV_OFFSET    26
#define IO_SUBCTRL_SRST_ST_NIC_RGMII_TX_LEN           2
#define IO_SUBCTRL_SRST_ST_NIC_RGMII_TX_OFFSET        24
#define IO_SUBCTRL_SRST_ST_NIC_PTP_LEN                4
#define IO_SUBCTRL_SRST_ST_NIC_PTP_OFFSET             20
#define IO_SUBCTRL_SRST_ST_NIC_XXVGE_CORE_SYNC_LEN    4
#define IO_SUBCTRL_SRST_ST_NIC_XXVGE_CORE_SYNC_OFFSET 16
#define IO_SUBCTRL_SRST_ST_NIC_XXVGE_CORE_LEN         4
#define IO_SUBCTRL_SRST_ST_NIC_XXVGE_CORE_OFFSET      12
#define IO_SUBCTRL_SRST_ST_NIC_XXVGE_CFG_LEN          4
#define IO_SUBCTRL_SRST_ST_NIC_XXVGE_CFG_OFFSET       8
#define IO_SUBCTRL_SRST_ST_NIC_XXVGE_PTP_SYNC_LEN     4
#define IO_SUBCTRL_SRST_ST_NIC_XXVGE_PTP_SYNC_OFFSET  4
#define IO_SUBCTRL_SRST_ST_NIC_XXVGE_TX_SDS_LEN       4
#define IO_SUBCTRL_SRST_ST_NIC_XXVGE_TX_SDS_OFFSET    0

#define IO_SUBCTRL_SRST_ST_NIC_MAG_APP_SYNC_LEN    1
#define IO_SUBCTRL_SRST_ST_NIC_MAG_APP_SYNC_OFFSET 7
#define IO_SUBCTRL_SRST_ST_NIC_MAG_APP_LEN         1
#define IO_SUBCTRL_SRST_ST_NIC_MAG_APP_OFFSET      6
#define IO_SUBCTRL_SRST_ST_NIC_MAG_CFG_LEN         1
#define IO_SUBCTRL_SRST_ST_NIC_MAG_CFG_OFFSET      5
#define IO_SUBCTRL_SRST_ST_NIC_SLV_LEN             1
#define IO_SUBCTRL_SRST_ST_NIC_SLV_OFFSET          4
#define IO_SUBCTRL_SRST_ST_NIC_COMMON_REG_LEN      1
#define IO_SUBCTRL_SRST_ST_NIC_COMMON_REG_OFFSET   3
#define IO_SUBCTRL_SRST_ST_NIC_COMMON_LEN          1
#define IO_SUBCTRL_SRST_ST_NIC_COMMON_OFFSET       2
#define IO_SUBCTRL_SRST_ST_NIC_PPE_REG_LEN         1
#define IO_SUBCTRL_SRST_ST_NIC_PPE_REG_OFFSET      1
#define IO_SUBCTRL_SRST_ST_NIC_PPE_LEN             1
#define IO_SUBCTRL_SRST_ST_NIC_PPE_OFFSET          0

#define IO_SUBCTRL_SRST_ST_PCIE0_LEN              1
#define IO_SUBCTRL_SRST_ST_PCIE0_OFFSET           22
#define IO_SUBCTRL_SRST_ST_PCIE0_AP_AXI_LEN       1
#define IO_SUBCTRL_SRST_ST_PCIE0_AP_AXI_OFFSET    21
#define IO_SUBCTRL_SRST_ST_PCIE0_APB_LEN          1
#define IO_SUBCTRL_SRST_ST_PCIE0_APB_OFFSET       20
#define IO_SUBCTRL_SRST_ST_PCIE0_CORE_PHY_LEN     1
#define IO_SUBCTRL_SRST_ST_PCIE0_CORE_PHY_OFFSET  19
#define IO_SUBCTRL_SRST_ST_PCIE0_CORE_TL_LEN      1
#define IO_SUBCTRL_SRST_ST_PCIE0_CORE_TL_OFFSET   18
#define IO_SUBCTRL_SRST_ST_PCIE0_PCS_LOGIC_LEN    1
#define IO_SUBCTRL_SRST_ST_PCIE0_PCS_LOGIC_OFFSET 17
#define IO_SUBCTRL_SRST_ST_PCIE0_TL_AXI_LEN       1
#define IO_SUBCTRL_SRST_ST_PCIE0_TL_AXI_OFFSET    16
#define IO_SUBCTRL_SRST_ST_PCIE0_PCS_RX_LEN       4
#define IO_SUBCTRL_SRST_ST_PCIE0_PCS_RX_OFFSET    12
#define IO_SUBCTRL_SRST_ST_PCIE0_PCS_TX_LEN       4
#define IO_SUBCTRL_SRST_ST_PCIE0_PCS_TX_OFFSET    8
#define IO_SUBCTRL_SRST_ST_PCIE0_PIPE_LEN         4
#define IO_SUBCTRL_SRST_ST_PCIE0_PIPE_OFFSET      4
#define IO_SUBCTRL_SRST_ST_PCIE0_PIPE_LANE_LEN    4
#define IO_SUBCTRL_SRST_ST_PCIE0_PIPE_LANE_OFFSET 0

#define IO_SUBCTRL_SRST_ST_PCIE1_LEN              1
#define IO_SUBCTRL_SRST_ST_PCIE1_OFFSET           22
#define IO_SUBCTRL_SRST_ST_PCIE1_AP_AXI_LEN       1
#define IO_SUBCTRL_SRST_ST_PCIE1_AP_AXI_OFFSET    21
#define IO_SUBCTRL_SRST_ST_PCIE1_APB_LEN          1
#define IO_SUBCTRL_SRST_ST_PCIE1_APB_OFFSET       20
#define IO_SUBCTRL_SRST_ST_PCIE1_CORE_PHY_LEN     1
#define IO_SUBCTRL_SRST_ST_PCIE1_CORE_PHY_OFFSET  19
#define IO_SUBCTRL_SRST_ST_PCIE1_CORE_TL_LEN      1
#define IO_SUBCTRL_SRST_ST_PCIE1_CORE_TL_OFFSET   18
#define IO_SUBCTRL_SRST_ST_PCIE1_PCS_LOGIC_LEN    1
#define IO_SUBCTRL_SRST_ST_PCIE1_PCS_LOGIC_OFFSET 17
#define IO_SUBCTRL_SRST_ST_PCIE1_TL_AXI_LEN       1
#define IO_SUBCTRL_SRST_ST_PCIE1_TL_AXI_OFFSET    16
#define IO_SUBCTRL_SRST_ST_PCIE1_PCS_RX_LEN       4
#define IO_SUBCTRL_SRST_ST_PCIE1_PCS_RX_OFFSET    12
#define IO_SUBCTRL_SRST_ST_PCIE1_PCS_TX_LEN       4
#define IO_SUBCTRL_SRST_ST_PCIE1_PCS_TX_OFFSET    8
#define IO_SUBCTRL_SRST_ST_PCIE1_PIPE_LEN         4
#define IO_SUBCTRL_SRST_ST_PCIE1_PIPE_OFFSET      4
#define IO_SUBCTRL_SRST_ST_PCIE1_PIPE_LANE_LEN    4
#define IO_SUBCTRL_SRST_ST_PCIE1_PIPE_LANE_OFFSET 0

#define IO_SUBCTRL_SRST_ST_PCIE2_LEN              1
#define IO_SUBCTRL_SRST_ST_PCIE2_OFFSET           22
#define IO_SUBCTRL_SRST_ST_PCIE2_AP_AXI_LEN       1
#define IO_SUBCTRL_SRST_ST_PCIE2_AP_AXI_OFFSET    21
#define IO_SUBCTRL_SRST_ST_PCIE2_APB_LEN          1
#define IO_SUBCTRL_SRST_ST_PCIE2_APB_OFFSET       20
#define IO_SUBCTRL_SRST_ST_PCIE2_CORE_PHY_LEN     1
#define IO_SUBCTRL_SRST_ST_PCIE2_CORE_PHY_OFFSET  19
#define IO_SUBCTRL_SRST_ST_PCIE2_CORE_TL_LEN      1
#define IO_SUBCTRL_SRST_ST_PCIE2_CORE_TL_OFFSET   18
#define IO_SUBCTRL_SRST_ST_PCIE2_PCS_LOGIC_LEN    1
#define IO_SUBCTRL_SRST_ST_PCIE2_PCS_LOGIC_OFFSET 17
#define IO_SUBCTRL_SRST_ST_PCIE2_TL_AXI_LEN       1
#define IO_SUBCTRL_SRST_ST_PCIE2_TL_AXI_OFFSET    16
#define IO_SUBCTRL_SRST_ST_PCIE2_PCS_RX_LEN       4
#define IO_SUBCTRL_SRST_ST_PCIE2_PCS_RX_OFFSET    12
#define IO_SUBCTRL_SRST_ST_PCIE2_PCS_TX_LEN       4
#define IO_SUBCTRL_SRST_ST_PCIE2_PCS_TX_OFFSET    8
#define IO_SUBCTRL_SRST_ST_PCIE2_PIPE_LEN         4
#define IO_SUBCTRL_SRST_ST_PCIE2_PIPE_OFFSET      4
#define IO_SUBCTRL_SRST_ST_PCIE2_PIPE_LANE_LEN    4
#define IO_SUBCTRL_SRST_ST_PCIE2_PIPE_LANE_OFFSET 0

#define IO_SUBCTRL_SRST_ST_PCIE3_LEN              1
#define IO_SUBCTRL_SRST_ST_PCIE3_OFFSET           22
#define IO_SUBCTRL_SRST_ST_PCIE3_AP_AXI_LEN       1
#define IO_SUBCTRL_SRST_ST_PCIE3_AP_AXI_OFFSET    21
#define IO_SUBCTRL_SRST_ST_PCIE3_APB_LEN          1
#define IO_SUBCTRL_SRST_ST_PCIE3_APB_OFFSET       20
#define IO_SUBCTRL_SRST_ST_PCIE3_CORE_PHY_LEN     1
#define IO_SUBCTRL_SRST_ST_PCIE3_CORE_PHY_OFFSET  19
#define IO_SUBCTRL_SRST_ST_PCIE3_CORE_TL_LEN      1
#define IO_SUBCTRL_SRST_ST_PCIE3_CORE_TL_OFFSET   18
#define IO_SUBCTRL_SRST_ST_PCIE3_PCS_LOGIC_LEN    1
#define IO_SUBCTRL_SRST_ST_PCIE3_PCS_LOGIC_OFFSET 17
#define IO_SUBCTRL_SRST_ST_PCIE3_TL_AXI_LEN       1
#define IO_SUBCTRL_SRST_ST_PCIE3_TL_AXI_OFFSET    16
#define IO_SUBCTRL_SRST_ST_PCIE3_PCS_RX_LEN       4
#define IO_SUBCTRL_SRST_ST_PCIE3_PCS_RX_OFFSET    12
#define IO_SUBCTRL_SRST_ST_PCIE3_PCS_TX_LEN       4
#define IO_SUBCTRL_SRST_ST_PCIE3_PCS_TX_OFFSET    8
#define IO_SUBCTRL_SRST_ST_PCIE3_PIPE_LEN         4
#define IO_SUBCTRL_SRST_ST_PCIE3_PIPE_OFFSET      4
#define IO_SUBCTRL_SRST_ST_PCIE3_PIPE_LANE_LEN    4
#define IO_SUBCTRL_SRST_ST_PCIE3_PIPE_LANE_OFFSET 0

#define IO_SUBCTRL_SRST_ST_RGMII_RX_LEN        2
#define IO_SUBCTRL_SRST_ST_RGMII_RX_OFFSET     6
#define IO_SUBCTRL_SRST_ST_RGMII_RX_INV_LEN    2
#define IO_SUBCTRL_SRST_ST_RGMII_RX_INV_OFFSET 4
#define IO_SUBCTRL_SRST_ST_RGMII_TX_LEN        2
#define IO_SUBCTRL_SRST_ST_RGMII_TX_OFFSET     2
#define IO_SUBCTRL_SRST_ST_RGMII_TX_INV_LEN    2
#define IO_SUBCTRL_SRST_ST_RGMII_TX_INV_OFFSET 0

#define IO_SUBCTRL_SRST_ST_HPM_LEN    1
#define IO_SUBCTRL_SRST_ST_HPM_OFFSET 0

#define IO_SUBCTRL_SRST_ST_SENSOR_LEN    1
#define IO_SUBCTRL_SRST_ST_SENSOR_OFFSET 0

#define IO_SUBCTRL_SRST_ST_BCBIST0_LEN    1
#define IO_SUBCTRL_SRST_ST_BCBIST0_OFFSET 0

#define IO_SUBCTRL_U3_VBUS_ENABLE_USB3_LEN        1
#define IO_SUBCTRL_U3_VBUS_ENABLE_USB3_OFFSET     31
#define IO_SUBCTRL_U3_LINK_CURR_STATE_USB3_LEN    7
#define IO_SUBCTRL_U3_LINK_CURR_STATE_USB3_OFFSET 24
#define IO_SUBCTRL_U3_VBUS_ENABLE_USB2_LEN        1
#define IO_SUBCTRL_U3_VBUS_ENABLE_USB2_OFFSET     23
#define IO_SUBCTRL_U3_LINK_CURR_STATE_USB2_LEN    7
#define IO_SUBCTRL_U3_LINK_CURR_STATE_USB2_OFFSET 16
#define IO_SUBCTRL_U3_VBUS_ENABLE_USB1_LEN        1
#define IO_SUBCTRL_U3_VBUS_ENABLE_USB1_OFFSET     15
#define IO_SUBCTRL_U3_LINK_CURR_STATE_USB1_LEN    7
#define IO_SUBCTRL_U3_LINK_CURR_STATE_USB1_OFFSET 8
#define IO_SUBCTRL_U3_VBUS_ENABLE_USB0_LEN        1
#define IO_SUBCTRL_U3_VBUS_ENABLE_USB0_OFFSET     7
#define IO_SUBCTRL_U3_LINK_CURR_STATE_USB0_LEN    7
#define IO_SUBCTRL_U3_LINK_CURR_STATE_USB0_OFFSET 0

#define IO_SUBCTRL_USBC_LOW_POWER_USB3_LEN    1
#define IO_SUBCTRL_USBC_LOW_POWER_USB3_OFFSET 3
#define IO_SUBCTRL_USBC_LOW_POWER_USB2_LEN    1
#define IO_SUBCTRL_USBC_LOW_POWER_USB2_OFFSET 2
#define IO_SUBCTRL_USBC_LOW_POWER_USB1_LEN    1
#define IO_SUBCTRL_USBC_LOW_POWER_USB1_OFFSET 1
#define IO_SUBCTRL_USBC_LOW_POWER_USB0_LEN    1
#define IO_SUBCTRL_USBC_LOW_POWER_USB0_OFFSET 0

#define IO_SUBCTRL_USB_BRG1_DLOCK_SLV_LEN     2
#define IO_SUBCTRL_USB_BRG1_DLOCK_SLV_OFFSET  13
#define IO_SUBCTRL_USB_BRG1_DLOCK_MST_LEN     4
#define IO_SUBCTRL_USB_BRG1_DLOCK_MST_OFFSET  9
#define IO_SUBCTRL_USB_BRG1_HIAXI_IDLE_LEN    1
#define IO_SUBCTRL_USB_BRG1_HIAXI_IDLE_OFFSET 8
#define IO_SUBCTRL_USB_BRG0_DLOCK_SLV_LEN     2
#define IO_SUBCTRL_USB_BRG0_DLOCK_SLV_OFFSET  5
#define IO_SUBCTRL_USB_BRG0_DLOCK_MST_LEN     4
#define IO_SUBCTRL_USB_BRG0_DLOCK_MST_OFFSET  1
#define IO_SUBCTRL_USB_BRG0_HIAXI_IDLE_LEN    1
#define IO_SUBCTRL_USB_BRG0_HIAXI_IDLE_OFFSET 0

#define IO_SUBCTRL_PHY_BIST_RESULT_LEN       3
#define IO_SUBCTRL_PHY_BIST_RESULT_OFFSET    15
#define IO_SUBCTRL_PHY_BIST_FINISH_LEN       3
#define IO_SUBCTRL_PHY_BIST_FINISH_OFFSET    12
#define IO_SUBCTRL_HSRXDAT_USBPHY_LEN        3
#define IO_SUBCTRL_HSRXDAT_USBPHY_OFFSET     9
#define IO_SUBCTRL_HSSQUELCH_USBPHY_LEN      3
#define IO_SUBCTRL_HSSQUELCH_USBPHY_OFFSET   6
#define IO_SUBCTRL_REF_CLK_REQ_USBPHY_LEN    3
#define IO_SUBCTRL_REF_CLK_REQ_USBPHY_OFFSET 3
#define IO_SUBCTRL_PLL_LOCK_USBPHY_LEN       3
#define IO_SUBCTRL_PLL_LOCK_USBPHY_OFFSET    0

#define IO_SUBCTRL_USB0_RAM0_ECC_ADDR_LEN         10
#define IO_SUBCTRL_USB0_RAM0_ECC_ADDR_OFFSET      20
#define IO_SUBCTRL_USB0_RAM0_ECC_ERR_SYN_LEN      16
#define IO_SUBCTRL_USB0_RAM0_ECC_ERR_SYN_OFFSET   2
#define IO_SUBCTRL_USB0_RAM0_ECC_MULTI_ERR_LEN    1
#define IO_SUBCTRL_USB0_RAM0_ECC_MULTI_ERR_OFFSET 1
#define IO_SUBCTRL_USB0_RAM0_ECC_ERR_LEN          1
#define IO_SUBCTRL_USB0_RAM0_ECC_ERR_OFFSET       0

#define IO_SUBCTRL_USB0_RAM1_ECC_ADDR_LEN         11
#define IO_SUBCTRL_USB0_RAM1_ECC_ADDR_OFFSET      20
#define IO_SUBCTRL_USB0_RAM1_ECC_ERR_SYN_LEN      16
#define IO_SUBCTRL_USB0_RAM1_ECC_ERR_SYN_OFFSET   2
#define IO_SUBCTRL_USB0_RAM1_ECC_MULTI_ERR_LEN    1
#define IO_SUBCTRL_USB0_RAM1_ECC_MULTI_ERR_OFFSET 1
#define IO_SUBCTRL_USB0_RAM1_ECC_ERR_LEN          1
#define IO_SUBCTRL_USB0_RAM1_ECC_ERR_OFFSET       0

#define IO_SUBCTRL_USB0_RAM2_ECC_ADDR_LEN         11
#define IO_SUBCTRL_USB0_RAM2_ECC_ADDR_OFFSET      20
#define IO_SUBCTRL_USB0_RAM2_ECC_ERR_SYN_LEN      16
#define IO_SUBCTRL_USB0_RAM2_ECC_ERR_SYN_OFFSET   2
#define IO_SUBCTRL_USB0_RAM2_ECC_MULTI_ERR_LEN    1
#define IO_SUBCTRL_USB0_RAM2_ECC_MULTI_ERR_OFFSET 1
#define IO_SUBCTRL_USB0_RAM2_ECC_ERR_LEN          1
#define IO_SUBCTRL_USB0_RAM2_ECC_ERR_OFFSET       0

#define IO_SUBCTRL_USB0_RAM3_ECC_ADDR_LEN         11
#define IO_SUBCTRL_USB0_RAM3_ECC_ADDR_OFFSET      20
#define IO_SUBCTRL_USB0_RAM3_ECC_ERR_SYN_LEN      16
#define IO_SUBCTRL_USB0_RAM3_ECC_ERR_SYN_OFFSET   2
#define IO_SUBCTRL_USB0_RAM3_ECC_MULTI_ERR_LEN    1
#define IO_SUBCTRL_USB0_RAM3_ECC_MULTI_ERR_OFFSET 1
#define IO_SUBCTRL_USB0_RAM3_ECC_ERR_LEN          1
#define IO_SUBCTRL_USB0_RAM3_ECC_ERR_OFFSET       0

#define IO_SUBCTRL_USB0_RAM4_ECC_ADDR_LEN         9
#define IO_SUBCTRL_USB0_RAM4_ECC_ADDR_OFFSET      18
#define IO_SUBCTRL_USB0_RAM4_ECC_ERR_SYN_LEN      9
#define IO_SUBCTRL_USB0_RAM4_ECC_ERR_SYN_OFFSET   2
#define IO_SUBCTRL_USB0_RAM4_ECC_MULTI_ERR_LEN    1
#define IO_SUBCTRL_USB0_RAM4_ECC_MULTI_ERR_OFFSET 1
#define IO_SUBCTRL_USB0_RAM4_ECC_ERR_LEN          1
#define IO_SUBCTRL_USB0_RAM4_ECC_ERR_OFFSET       0

#define IO_SUBCTRL_USB1_RAM0_ECC_ADDR_LEN         10
#define IO_SUBCTRL_USB1_RAM0_ECC_ADDR_OFFSET      20
#define IO_SUBCTRL_USB1_RAM0_ECC_ERR_SYN_LEN      16
#define IO_SUBCTRL_USB1_RAM0_ECC_ERR_SYN_OFFSET   2
#define IO_SUBCTRL_USB1_RAM0_ECC_MULTI_ERR_LEN    1
#define IO_SUBCTRL_USB1_RAM0_ECC_MULTI_ERR_OFFSET 1
#define IO_SUBCTRL_USB1_RAM0_ECC_ERR_LEN          1
#define IO_SUBCTRL_USB1_RAM0_ECC_ERR_OFFSET       0

#define IO_SUBCTRL_USB1_RAM1_ECC_ADDR_LEN         11
#define IO_SUBCTRL_USB1_RAM1_ECC_ADDR_OFFSET      20
#define IO_SUBCTRL_USB1_RAM1_ECC_ERR_SYN_LEN      16
#define IO_SUBCTRL_USB1_RAM1_ECC_ERR_SYN_OFFSET   2
#define IO_SUBCTRL_USB1_RAM1_ECC_MULTI_ERR_LEN    1
#define IO_SUBCTRL_USB1_RAM1_ECC_MULTI_ERR_OFFSET 1
#define IO_SUBCTRL_USB1_RAM1_ECC_ERR_LEN          1
#define IO_SUBCTRL_USB1_RAM1_ECC_ERR_OFFSET       0

#define IO_SUBCTRL_USB1_RAM2_ECC_ADDR_LEN         11
#define IO_SUBCTRL_USB1_RAM2_ECC_ADDR_OFFSET      20
#define IO_SUBCTRL_USB1_RAM2_ECC_ERR_SYN_LEN      16
#define IO_SUBCTRL_USB1_RAM2_ECC_ERR_SYN_OFFSET   2
#define IO_SUBCTRL_USB1_RAM2_ECC_MULTI_ERR_LEN    1
#define IO_SUBCTRL_USB1_RAM2_ECC_MULTI_ERR_OFFSET 1
#define IO_SUBCTRL_USB1_RAM2_ECC_ERR_LEN          1
#define IO_SUBCTRL_USB1_RAM2_ECC_ERR_OFFSET       0

#define IO_SUBCTRL_USB1_RAM3_ECC_ADDR_LEN         11
#define IO_SUBCTRL_USB1_RAM3_ECC_ADDR_OFFSET      20
#define IO_SUBCTRL_USB1_RAM3_ECC_ERR_SYN_LEN      16
#define IO_SUBCTRL_USB1_RAM3_ECC_ERR_SYN_OFFSET   2
#define IO_SUBCTRL_USB1_RAM3_ECC_MULTI_ERR_LEN    1
#define IO_SUBCTRL_USB1_RAM3_ECC_MULTI_ERR_OFFSET 1
#define IO_SUBCTRL_USB1_RAM3_ECC_ERR_LEN          1
#define IO_SUBCTRL_USB1_RAM3_ECC_ERR_OFFSET       0

#define IO_SUBCTRL_USB1_RAM4_ECC_ADDR_LEN         9
#define IO_SUBCTRL_USB1_RAM4_ECC_ADDR_OFFSET      18
#define IO_SUBCTRL_USB1_RAM4_ECC_ERR_SYN_LEN      9
#define IO_SUBCTRL_USB1_RAM4_ECC_ERR_SYN_OFFSET   2
#define IO_SUBCTRL_USB1_RAM4_ECC_MULTI_ERR_LEN    1
#define IO_SUBCTRL_USB1_RAM4_ECC_MULTI_ERR_OFFSET 1
#define IO_SUBCTRL_USB1_RAM4_ECC_ERR_LEN          1
#define IO_SUBCTRL_USB1_RAM4_ECC_ERR_OFFSET       0

#define IO_SUBCTRL_USB2_RAM0_ECC_ADDR_LEN         10
#define IO_SUBCTRL_USB2_RAM0_ECC_ADDR_OFFSET      20
#define IO_SUBCTRL_USB2_RAM0_ECC_ERR_SYN_LEN      16
#define IO_SUBCTRL_USB2_RAM0_ECC_ERR_SYN_OFFSET   2
#define IO_SUBCTRL_USB2_RAM0_ECC_MULTI_ERR_LEN    1
#define IO_SUBCTRL_USB2_RAM0_ECC_MULTI_ERR_OFFSET 1
#define IO_SUBCTRL_USB2_RAM0_ECC_ERR_LEN          1
#define IO_SUBCTRL_USB2_RAM0_ECC_ERR_OFFSET       0

#define IO_SUBCTRL_USB2_RAM1_ECC_ADDR_LEN         11
#define IO_SUBCTRL_USB2_RAM1_ECC_ADDR_OFFSET      20
#define IO_SUBCTRL_USB2_RAM1_ECC_ERR_SYN_LEN      16
#define IO_SUBCTRL_USB2_RAM1_ECC_ERR_SYN_OFFSET   2
#define IO_SUBCTRL_USB2_RAM1_ECC_MULTI_ERR_LEN    1
#define IO_SUBCTRL_USB2_RAM1_ECC_MULTI_ERR_OFFSET 1
#define IO_SUBCTRL_USB2_RAM1_ECC_ERR_LEN          1
#define IO_SUBCTRL_USB2_RAM1_ECC_ERR_OFFSET       0

#define IO_SUBCTRL_USB2_RAM2_ECC_ADDR_LEN         11
#define IO_SUBCTRL_USB2_RAM2_ECC_ADDR_OFFSET      20
#define IO_SUBCTRL_USB2_RAM2_ECC_ERR_SYN_LEN      16
#define IO_SUBCTRL_USB2_RAM2_ECC_ERR_SYN_OFFSET   2
#define IO_SUBCTRL_USB2_RAM2_ECC_MULTI_ERR_LEN    1
#define IO_SUBCTRL_USB2_RAM2_ECC_MULTI_ERR_OFFSET 1
#define IO_SUBCTRL_USB2_RAM2_ECC_ERR_LEN          1
#define IO_SUBCTRL_USB2_RAM2_ECC_ERR_OFFSET       0

#define IO_SUBCTRL_USB2_RAM3_ECC_ADDR_LEN         11
#define IO_SUBCTRL_USB2_RAM3_ECC_ADDR_OFFSET      20
#define IO_SUBCTRL_USB2_RAM3_ECC_ERR_SYN_LEN      16
#define IO_SUBCTRL_USB2_RAM3_ECC_ERR_SYN_OFFSET   2
#define IO_SUBCTRL_USB2_RAM3_ECC_MULTI_ERR_LEN    1
#define IO_SUBCTRL_USB2_RAM3_ECC_MULTI_ERR_OFFSET 1
#define IO_SUBCTRL_USB2_RAM3_ECC_ERR_LEN          1
#define IO_SUBCTRL_USB2_RAM3_ECC_ERR_OFFSET       0

#define IO_SUBCTRL_USB2_RAM4_ECC_ADDR_LEN         9
#define IO_SUBCTRL_USB2_RAM4_ECC_ADDR_OFFSET      18
#define IO_SUBCTRL_USB2_RAM4_ECC_ERR_SYN_LEN      9
#define IO_SUBCTRL_USB2_RAM4_ECC_ERR_SYN_OFFSET   2
#define IO_SUBCTRL_USB2_RAM4_ECC_MULTI_ERR_LEN    1
#define IO_SUBCTRL_USB2_RAM4_ECC_MULTI_ERR_OFFSET 1
#define IO_SUBCTRL_USB2_RAM4_ECC_ERR_LEN          1
#define IO_SUBCTRL_USB2_RAM4_ECC_ERR_OFFSET       0

#define IO_SUBCTRL_USB3_RAM0_ECC_ADDR_LEN         10
#define IO_SUBCTRL_USB3_RAM0_ECC_ADDR_OFFSET      20
#define IO_SUBCTRL_USB3_RAM0_ECC_ERR_SYN_LEN      16
#define IO_SUBCTRL_USB3_RAM0_ECC_ERR_SYN_OFFSET   2
#define IO_SUBCTRL_USB3_RAM0_ECC_MULTI_ERR_LEN    1
#define IO_SUBCTRL_USB3_RAM0_ECC_MULTI_ERR_OFFSET 1
#define IO_SUBCTRL_USB3_RAM0_ECC_ERR_LEN          1
#define IO_SUBCTRL_USB3_RAM0_ECC_ERR_OFFSET       0

#define IO_SUBCTRL_USB3_RAM1_ECC_ADDR_LEN         11
#define IO_SUBCTRL_USB3_RAM1_ECC_ADDR_OFFSET      20
#define IO_SUBCTRL_USB3_RAM1_ECC_ERR_SYN_LEN      16
#define IO_SUBCTRL_USB3_RAM1_ECC_ERR_SYN_OFFSET   2
#define IO_SUBCTRL_USB3_RAM1_ECC_MULTI_ERR_LEN    1
#define IO_SUBCTRL_USB3_RAM1_ECC_MULTI_ERR_OFFSET 1
#define IO_SUBCTRL_USB3_RAM1_ECC_ERR_LEN          1
#define IO_SUBCTRL_USB3_RAM1_ECC_ERR_OFFSET       0

#define IO_SUBCTRL_USB3_RAM2_ECC_ADDR_LEN         11
#define IO_SUBCTRL_USB3_RAM2_ECC_ADDR_OFFSET      20
#define IO_SUBCTRL_USB3_RAM2_ECC_ERR_SYN_LEN      16
#define IO_SUBCTRL_USB3_RAM2_ECC_ERR_SYN_OFFSET   2
#define IO_SUBCTRL_USB3_RAM2_ECC_MULTI_ERR_LEN    1
#define IO_SUBCTRL_USB3_RAM2_ECC_MULTI_ERR_OFFSET 1
#define IO_SUBCTRL_USB3_RAM2_ECC_ERR_LEN          1
#define IO_SUBCTRL_USB3_RAM2_ECC_ERR_OFFSET       0

#define IO_SUBCTRL_USB3_RAM3_ECC_ADDR_LEN         11
#define IO_SUBCTRL_USB3_RAM3_ECC_ADDR_OFFSET      20
#define IO_SUBCTRL_USB3_RAM3_ECC_ERR_SYN_LEN      16
#define IO_SUBCTRL_USB3_RAM3_ECC_ERR_SYN_OFFSET   2
#define IO_SUBCTRL_USB3_RAM3_ECC_MULTI_ERR_LEN    1
#define IO_SUBCTRL_USB3_RAM3_ECC_MULTI_ERR_OFFSET 1
#define IO_SUBCTRL_USB3_RAM3_ECC_ERR_LEN          1
#define IO_SUBCTRL_USB3_RAM3_ECC_ERR_OFFSET       0

#define IO_SUBCTRL_USB3_RAM4_ECC_ADDR_LEN         9
#define IO_SUBCTRL_USB3_RAM4_ECC_ADDR_OFFSET      18
#define IO_SUBCTRL_USB3_RAM4_ECC_ERR_SYN_LEN      9
#define IO_SUBCTRL_USB3_RAM4_ECC_ERR_SYN_OFFSET   2
#define IO_SUBCTRL_USB3_RAM4_ECC_MULTI_ERR_LEN    1
#define IO_SUBCTRL_USB3_RAM4_ECC_MULTI_ERR_OFFSET 1
#define IO_SUBCTRL_USB3_RAM4_ECC_ERR_LEN          1
#define IO_SUBCTRL_USB3_RAM4_ECC_ERR_OFFSET       0

#define IO_SUBCTRL_TSENSOR_TEMP_INNER_CLK_OK_LEN    1
#define IO_SUBCTRL_TSENSOR_TEMP_INNER_CLK_OK_OFFSET 20
#define IO_SUBCTRL_TSENSOR_TEMP_INNER_CLK_LEN       1
#define IO_SUBCTRL_TSENSOR_TEMP_INNER_CLK_OFFSET    19
#define IO_SUBCTRL_TSENSOR_TEMP_READY_LEN           1
#define IO_SUBCTRL_TSENSOR_TEMP_READY_OFFSET        18
#define IO_SUBCTRL_TSENSOR_TEMP_OUT_LEN             16
#define IO_SUBCTRL_TSENSOR_TEMP_OUT_OFFSET          0

#define IO_SUBCTRL_FLAG_NOW_BCBIST0_LEN    1
#define IO_SUBCTRL_FLAG_NOW_BCBIST0_OFFSET 1
#define IO_SUBCTRL_FLAG_BCBIST0_LEN        1
#define IO_SUBCTRL_FLAG_BCBIST0_OFFSET     0

#define IO_SUBCTRL_TSENSOR_LOCAL_REMOTE_TIMEOUT_PULSE_STATUS_LEN      2
#define IO_SUBCTRL_TSENSOR_LOCAL_REMOTE_TIMEOUT_PULSE_STATUS_OFFSET   6
#define IO_SUBCTRL_TSENSOR_LOCAL_REMOTE_ULTRAOVER_PULSE_STATUS_LEN    2
#define IO_SUBCTRL_TSENSOR_LOCAL_REMOTE_ULTRAOVER_PULSE_STATUS_OFFSET 4
#define IO_SUBCTRL_TSENSOR_LOCAL_REMOTE_OVER_PULSE_STATUS_LEN         2
#define IO_SUBCTRL_TSENSOR_LOCAL_REMOTE_OVER_PULSE_STATUS_OFFSET      2
#define IO_SUBCTRL_TSENSOR_LOCAL_REMOTE_UNDER_PULSE_STATUS_LEN        2
#define IO_SUBCTRL_TSENSOR_LOCAL_REMOTE_UNDER_PULSE_STATUS_OFFSET     0

#define IO_SUBCTRL_SYSCTRL_LOCK_LEN    32
#define IO_SUBCTRL_SYSCTRL_LOCK_OFFSET 0

#define IO_SUBCTRL_SYSCTRL_UNLOCK_LEN    32
#define IO_SUBCTRL_SYSCTRL_UNLOCK_OFFSET 0

#define IO_SUBCTRL_IOMUX_TZPC_SEL0_LEN    32
#define IO_SUBCTRL_IOMUX_TZPC_SEL0_OFFSET 0

#define IO_SUBCTRL_IOMUX_TZPC_SEL1_LEN    32
#define IO_SUBCTRL_IOMUX_TZPC_SEL1_OFFSET 0

#define IO_SUBCTRL_PROBE_MUX_SEL_LEN    4
#define IO_SUBCTRL_PROBE_MUX_SEL_OFFSET 0

#define IO_SUBCTRL_SMMU_ICG_EN_SRST_REQ_SEC_ATTR_SWITCHER_LEN    1
#define IO_SUBCTRL_SMMU_ICG_EN_SRST_REQ_SEC_ATTR_SWITCHER_OFFSET 0

#define IO_SUBCTRL_ECO_RSV0_SUBCTRL_LEN    32
#define IO_SUBCTRL_ECO_RSV0_SUBCTRL_OFFSET 0

#define IO_SUBCTRL_ECO_RSV1_SUBCTRL_LEN    32
#define IO_SUBCTRL_ECO_RSV1_SUBCTRL_OFFSET 0

#define IO_SUBCTRL_ECO_RSV2_SUBCTRL_LEN    32
#define IO_SUBCTRL_ECO_RSV2_SUBCTRL_OFFSET 0

#define IO_SUBCTRL_ECO_RSV3_SUBCTRL_LEN    32
#define IO_SUBCTRL_ECO_RSV3_SUBCTRL_OFFSET 0

#define IO_SUBCTRL_ECO_RSV4_SUBCTRL_LEN    32
#define IO_SUBCTRL_ECO_RSV4_SUBCTRL_OFFSET 0

#define IO_SUBCTRL_ECO_RSV5_SUBCTRL_LEN    32
#define IO_SUBCTRL_ECO_RSV5_SUBCTRL_OFFSET 0

#define IO_SUBCTRL_VER_NUM_LEN    32
#define IO_SUBCTRL_VER_NUM_OFFSET 0

#endif // IO_SUBCTRL_REG_OFFSET_FIELD_H
